Side-by-side comparison
| Parameter | PLA | PROM |
|---|---|---|
| Full Form | Programmable Logic Array | PROM: Programmable ROM | PLD: Programmable Logic Device (umbrella) |
| AND Plane | Programmable | PROM: Fixed (decoder — all minterms) | PAL: Programmable | GAL: Programmable |
| OR Plane | Programmable | PROM: Programmable | PAL: Fixed | GAL: Programmable |
| Product Terms per Output | Shared product terms across all outputs | PROM: all minterms available | PAL: fixed set per output (e.g. 8) |
| Typical IC | PLA: custom/ASIC cell | PROM: 82S100 | PAL: PAL16L8 | GAL: GAL22V10 |
| Reprogrammable | No (mask-programmed in ASICs) | PROM: OTP (one-time) | PAL16L8: OTP | GAL22V10: EEPROM, ~100 erase cycles |
| Speed (propagation delay) | ~25 ns (depends on technology) | PAL16L8: ~15 ns | GAL22V10: ~5 ns |
| Output Macrocell | No registered outputs in basic PLA | GAL22V10: OLMC (Output Logic Macrocell) — combinational or registered |
| Use in Design | Sum-of-products logic, state machines in ASICs | PROM: LUT/ROM-based logic | PAL/GAL: glue logic replacement |
| Modern Equivalent | FPGA LUT | CPLD (e.g. Xilinx XC9500) or small FPGA |
Key differences
PLA has both AND and OR planes programmable — maximum flexibility, any sum-of-products function, but slower (~25 ns) and used mainly inside ASICs. PROM fixes the AND plane as a full decoder (all 2^n minterms present) and lets you program only the OR plane — every possible minterm is available, making it a universal logic element but wasteful for sparse functions. PAL (PAL16L8) fixes the OR plane and lets you program the AND plane — fast (~15 ns) but each output gets a fixed number of product terms. GAL22V10 adds EEPROM reprogrammability and an OLMC macrocell that switches between combinational and registered output, making it the most practical of the three for lab and field use.
When to use PLA
Use PROM (82S100) when implementing a truth-table-based function where the output for every minterm combination must be individually specified, such as a code converter or a character generator ROM.
When to use PROM
Use GAL22V10 when replacing multiple 74-series SSI/MSI chips with a single reprogrammable device, as its EEPROM cells allow multiple iterations during prototyping and its OLMC supports both combinational and registered outputs.
Recommendation
For university exams, choose PROM when asked about a ROM-based logic implementation — map the truth table directly to the OR plane. Choose PLA when the question asks about programmable AND and OR planes. For any practical lab replacement of glue logic, choose the GAL22V10.
Exam tip: GATE and university exams test PLA minimisation — given a Boolean function, draw the PLA diagram showing the minimum product terms in the AND plane and their connections to the OR plane outputs.
Interview tip: Interviewers at VLSI and FPGA companies ask how PLDs evolved into CPLDs and FPGAs — explain that the GAL macrocell concept scaled into the Xilinx XC9500 CPLD, which replaced discrete PALs in complex glue-logic designs.