GPIO Interview Questions

Q1. What is a GPIO pin and what are its basic operating modes?

A GPIO (General Purpose Input/Output) pin is a configurable digital I/O pin on a microcontroller that can be set as input (high impedance), output (push-pull or open-drain), or alternate function (UART, SPI, I2C, timers). An STM32F4 GPIO pin can source or sink 25 mA in push-pull output mode, and its output speed can be set to 2/25/50/100 MHz to balance switching speed against EMI. Understanding the distinction between these modes is fundamental to writing any firmware because incorrect mode selection is the most common cause of GPIO-related hardware bugs, such as bus contention or floating inputs.

Follow-up: What is the difference between push-pull and open-drain output modes?

Q2. What is the difference between push-pull and open-drain output?

In push-pull mode, the GPIO pin actively drives both logic high (VDD) and logic low (GND) using complementary P-channel and N-channel transistors inside the MCU; in open-drain mode, the pin can only pull low (N-channel FET pulls to GND) or float (FET off), requiring an external pull-up resistor to achieve logic high. I2C (SDA and SCL) uses open-drain because multiple devices share the same lines and any device can pull the bus low without two outputs fighting — with push-pull, two devices driving opposite states would cause latch-up or damage. Open-drain with 4.7 kΩ pull-up to 5 V on an NXP LPC1768 allows 5 V logic interfacing from a 3.3 V MCU because the MCU never drives the pin high.

Follow-up: Why does I2C require open-drain outputs and not push-pull?

Q3. What is a pull-up and pull-down resistor and when do you use each?

A pull-up resistor connects the GPIO input to VDD through a resistor (typically 10 kΩ), ensuring a defined logic-high state when no external signal drives the pin; a pull-down connects to GND, ensuring a defined logic-low default. On an STM32 GPIO input connected to a push-button that shorts the pin to GND when pressed, an internal pull-up (activated by setting GPIO_PUPDR to 01) prevents the input from floating to an undefined voltage when the button is released. Choosing pull-up vs pull-down depends on the active polarity of the signal — a button-to-GND needs pull-up; a button-to-VDD needs pull-down; failure to add any pull results in random values being read on the floating input.

Follow-up: What problems can occur if a GPIO input is left floating without any pull resistor?

Q4. How do you configure a GPIO interrupt on STM32?

On STM32, GPIO interrupts are configured by selecting the source GPIO port for the EXTI line via SYSCFG_EXTICR, setting the trigger edge (rising, falling, or both) in EXTI_RTSR and EXTI_FTSR, unmasking the line in EXTI_IMR, enabling the EXTI interrupt in NVIC, and writing the ISR name matching the EXTI vector (e.g., EXTI0_IRQHandler for pin 0). On an STM32F103, a 100 Hz reed switch on PA3 triggers EXTI3 on falling edge; the ISR calls HAL_GPIO_ReadPin to confirm the state and debounces in software using a 10 ms timer. Only one GPIO pin per EXTI line number can be active at a time — PA3 and PB3 both map to EXTI3, so only one can generate interrupts simultaneously.

Follow-up: What is the EXTI line sharing limitation on STM32 and how do you work around it when multiple pins on different ports share the same line number?

Q5. What is GPIO debouncing and how do you implement it?

Debouncing eliminates the multiple fast transitions (bouncing) a mechanical switch produces for 5–50 ms after contact, which a microcontroller reads as multiple button presses without filtering. Hardware debounce uses an RC filter (R = 10 kΩ, C = 100 nF giving 1 ms time constant) before the GPIO input; software debounce checks the pin state in a timer ISR every 10–20 ms and registers a press only if the state is stable for two or three consecutive samples. An STM32 GPIO interrupt approach — noting the first edge time with DWT cycle counter and ignoring subsequent interrupts within 50 ms — is faster to implement and saves external components for non-safety-critical applications.

Follow-up: What is the minimum debounce time typically required for a standard tactile push-button and how do you measure it?

Q6. How do you configure a GPIO as analog input for ADC use?

Setting a GPIO pin to analog mode (GPIO_MODE_ANALOG on STM32 HAL) disconnects the pin from the digital input Schmitt trigger, eliminating digital switching noise in the analog sampling path, and reduces current consumption by disabling the input buffer. On STM32F4, PA0 must be configured as GPIO_MODE_ANALOG before initializing ADC1 Channel 0; connecting a 0–3.3 V signal from a temperature sensor (e.g., NTC with 10 kΩ divider) to PA0 and reading with 12-bit ADC gives 4096 counts across 3.3 V, or about 0.8 mV per LSB. If the GPIO is left in digital mode while used as ADC input, the Schmitt trigger causes distortion and additional leakage at voltages near the switching threshold (~1.5 V).

Follow-up: What is the sampling time setting in STM32 ADC and why does it matter for high-impedance signal sources?

Q7. What is the GPIO output speed setting and why does it matter?

GPIO output speed on STM32 (Low/Medium/Fast/High: 2/25/50/100 MHz slew rate) controls how fast the output voltage transitions, affecting EMI generated by the pin, the drive capability at high frequency, and power consumption during switching. A 100 MHz GPIO toggle driving a 10 pF load dissipates approximately f × C × V² = 100M × 10p × 3.3² ≈ 10.9 mW per pin — negligible for a few pins but significant for a 40-bit parallel LCD interface. Setting unnecessary pins to high speed is a common firmware mistake that increases EMI and fails FCC/CE certification; pins should be set to the minimum speed sufficient for the signal's required rise time.

Follow-up: What is the relationship between GPIO output speed and the rise/fall time of the output voltage?

Q8. What is the maximum current a typical GPIO pin can source or sink?

A typical STM32 GPIO pin can source or sink up to 25 mA in push-pull output mode; the cumulative current across all I/O pins must not exceed 120 mA for the VDD1 domain on an STM32F4. Directly driving a standard red LED (1.8 V forward voltage, 20 mA) from PA5 on an STM32F103 requires a series resistor R = (3.3 - 1.8) / 0.02 = 75 Ω — choosing 82 Ω limits current to 18.3 mA, safely within the 25 mA limit. For loads above 25 mA (motors, relays, high-brightness LEDs), a transistor (2N2222 for ~600 mA) or MOSFET (IRLML2502 for up to 4 A) driven by the GPIO is mandatory.

Follow-up: What is the difference between absolute maximum current rating and the recommended operating current for GPIO pins?

Q9. What is a bidirectional GPIO and how is it used for bit-banging 1-wire protocol?

A bidirectional GPIO alternates between output-low (to drive the bus low) and input-high-impedance (to release the bus and read, relying on the external pull-up) within the same communication transaction, implementing open-drain behavior in software even on push-pull pins if the output never drives high. Dallas/Maxim DS18B20 1-wire temperature sensor is interfaced on STM32 by bit-banging: pull PA6 low for 480 µs (reset), switch to input, detect device presence pulse at 60–240 µs, then generate precise 60 µs read/write slots. Timing accuracy to ±2 µs requires disabling interrupts during each slot on a Cortex-M4 at 168 MHz to prevent jitter from preempting the bit-bang delays.

Follow-up: What is the maximum cable length for a 1-wire bus and what determines this limit?

Q10. What is the AFIO (alternate function I/O) remapping on STM32 and why is it used?

AFIO remapping assigns the alternate function of a peripheral (UART TX/RX, SPI CLK/MOSI, etc.) to an alternative set of GPIO pins, allowing board designers to route PCB traces more efficiently or avoid conflicts with other peripherals on the default pins. On STM32F103, USART1 TX is by default on PA9 and can be remapped to PB6 via AFIO_MAPR, which is essential when PA9 is occupied by the USB D+ pull-up in some boards. STM32F4 and later use a flexible 4-bit alternate function field (AFR) in each GPIO register, selecting from AF0–AF15 for each pin, replacing the single-bit AFIO remapping model of the older F1 series.

Follow-up: How does the GPIO alternate function (AF) register work on STM32F4 and how many AF options are available per pin?

Q11. How does GPIO output latency and determinism compare to hardware peripherals on an MCU?

GPIO driven from software in a polling loop has non-deterministic timing because ISR preemption and instruction pipeline effects can introduce jitter of 0–tens of microseconds; hardware peripherals (TIM, DMA, SPI) operate independently of the CPU and produce deterministic, cycle-accurate timing. A software-toggled GPIO in an STM32F4 main loop produces a waveform with ±0.5 µs jitter at 168 MHz; using TIM3 in PWM output compare mode on the same pin produces a waveform accurate to ±1/168 MHz = ±6 ns. For I2S audio, SPI transfers, and stepper motor step pulses, always use hardware peripheral output rather than software GPIO toggling to achieve timing precision.

Follow-up: What is DMA-driven GPIO toggling and how does it achieve precise multi-bit waveform generation?

Q12. What is the GPIO lock mechanism on STM32 and when should it be used?

The GPIO lock mechanism (LCKR register on STM32) prevents accidental reconfiguration of critical GPIO pins during runtime by writing a specific key sequence (write 1, write 0, write 1, read back 1 in LCKK) that freezes the configuration of selected pins until the next reset. Safety-critical outputs — such as the IGBT gate driver enable pin or a relay driver output — should be locked after initialization to prevent firmware bugs or stack corruption from accidentally changing pin mode, which could cause a short circuit or actuator misfire. Locks are one-time per reset; once locked, even privileged code cannot change the pin configuration without a hardware reset.

Follow-up: What safety standard context would require GPIO locking as part of a software safety mechanism?

Q13. What is the difference between internal and external pull-up resistors for I2C GPIO?

Internal pull-up resistors on STM32 are weak (nominally 40 kΩ) and suitable only for very short, low-speed I2C buses at 100 kHz on a PCB with minimal capacitance; I2C specification recommends external pull-ups sized to achieve the required rise time given bus capacitance, typically 4.7 kΩ for 100 kHz or 1 kΩ for 400 kHz on a 100 pF bus. An STM32 I2C bus with 10 cm PCB trace and three I2C devices has about 50 pF load; 4.7 kΩ pull-up gives a rise time of 4.7k × 50p = 235 ns, well within I2C Fast mode 300 ns maximum. Using internal 40 kΩ pull-ups on the same bus gives rise time of 2 µs — far exceeding the 400 kHz maximum, causing bus errors.

Follow-up: What is the maximum I2C pull-up resistor value for a given bus capacitance according to UM10204?

Q14. How do you use a GPIO to detect supply voltage brownout without an external ADC?

STM32 and most modern MCUs include a Programmable Voltage Detector (PVD) connected internally that asserts a GPIO EXTI interrupt or sets a status bit when VDD falls below a programmable threshold (1.9–2.9 V in 100 mV steps via PWR_CR on STM32F4). In a battery-powered sensor node, the PVD is set to 2.8 V; the PVD interrupt ISR writes a non-volatile state flag to flash or EEPROM and gracefully shuts down peripherals before VDD falls low enough to corrupt memory. This is far faster and more reliable than reading a resistor-divided supply with ADC — a BOR (Brown-Out Reset) catches extreme cases but PVD allows graceful shutdown before reset occurs.

Follow-up: What is the difference between PVD (Programmable Voltage Detector) and BOR (Brown-Out Reset) in STM32?

Q15. What is the GPIO electrical characteristics tolerance for 5V-tolerant pins?

5V-tolerant GPIO pins on STM32 (labelled FT in the datasheet pin table) can accept input voltages up to 5.5 V on their input while the MCU runs at 3.3 V, because the input stage uses a clamp or shifted threshold that handles the higher voltage without damage. On STM32F4, most GPIO pins are 5V-tolerant except those connected to the ADC, DAC, or RESET; connecting a 5 V UART level directly to a non-FT pin risks latching up the ESD protection diode and permanently damaging the MCU. The threshold voltages for logic-high input recognition on a 3.3 V STM32 GPIO are VIH = 0.7 × VDD = 2.31 V and VIL = 0.3 × VDD = 0.99 V, matching TTL logic levels for interoperability.

Follow-up: Why can't all GPIO pins on STM32 be 5V-tolerant even though 5V tolerance would be universally convenient?