I2C Interview Questions

Q1. What is I2C and what are its key characteristics?

I2C (Inter-Integrated Circuit) is a two-wire synchronous serial protocol using SDA (serial data) and SCL (serial clock), supporting multiple masters and up to 127 devices (7-bit address) or 1023 devices (10-bit) on a single bus with speeds of 100 kHz (standard), 400 kHz (fast), 1 MHz (fast-plus), and 3.4 MHz (high-speed mode). An STM32F4 I2C1 bus with a BME280 environmental sensor (address 0x76) and MPU-6050 IMU (address 0x68) shares just SDA (PB7) and SCL (PB6) with 4.7 kΩ pull-ups to 3.3 V. The two-wire bus, built-in addressing, and ACK/NACK mechanism make I2C ideal for short-distance board-level sensor interfacing, though it is slower and more complex than SPI for high-throughput applications.

Follow-up: What is the maximum number of devices on an I2C bus and what limits this in practice?

Q2. Explain the I2C start condition, stop condition, and ACK/NACK.

Start condition: SDA falls while SCL is high — this is the only time SDA changes with SCL high during a transaction. Stop condition: SDA rises while SCL is high — signals end of transaction and releases the bus. ACK: receiver pulls SDA low during the 9th clock pulse to acknowledge a received byte; NACK: receiver leaves SDA high (or releases it), indicating it did not receive the byte or wants to end the read transaction. When an STM32 reads the last byte from a BMP388 pressure sensor, it sends NACK on the last byte's ACK clock to signal the sensor to stop transmitting — sending ACK instead would hang the bus waiting for more data.

Follow-up: What happens to the I2C bus if a slave holds SDA low permanently due to a power glitch during a transaction?

Q3. What is the I2C 7-bit address format and how is a read/write transaction structured?

A 7-bit I2C address occupies bits 7:1 of the first byte after START, with bit 0 being the R/W flag (0 = write, 1 = read); the master sends this address byte and all devices on the bus check if it matches their own address, responding with ACK if it does. Reading register 0x3B from an MPU-6050 (address 0x68): START → 0xD0 (0x68<<1 | 0, write) → ACK → 0x3B (register) → ACK → REPEATED START → 0xD1 (0x68<<1 | 1, read) → data byte → NACK → STOP. The repeated start (Sr) avoids releasing the bus between the write phase (address selection) and read phase, preventing another master from seizing the bus in multi-master systems.

Follow-up: What is a repeated start condition and when is it essential to use it instead of a stop followed by a new start?

Q4. How do you size the pull-up resistors for an I2C bus?

I2C pull-up resistance is chosen so that Rpull_up × Cbus ≤ T_rise_max, where T_rise_max = 300 ns for fast mode (400 kHz) and Cbus is the total capacitance of SDA or SCL. For a 100 pF bus (two sensors + 5 cm PCB trace), Rmax = 300 ns / 100 pF = 3 kΩ; standard 4.7 kΩ works for standard mode but requires checking against actual rise time measurement at 400 kHz fast mode. I2C specification (UM10204) also sets a minimum resistance Rmin = (VDD - VOL_max) / IOL_max = (3.3 - 0.4) / 3 mA = 967 Ω to ensure the open-drain driver can pull the bus below VOL_max when asserting low.

Follow-up: What is the I2C bus capacitance specification and how do you measure it in the field?

Q5. What is clock stretching in I2C and why do some slaves use it?

Clock stretching allows an I2C slave to hold SCL low after the master releases it, pausing the transaction to give the slave time to process data or prepare a response; the master must detect this and wait, extending the clock period until SCL is released by the slave. An SHT31 humidity sensor stretches the clock for 2–15 ms after receiving a measurement command while the sensor integrates the reading, during which the master must not timeout and abort. Some I2C masters (including certain STM32 HAL implementations) have a maximum clock stretch timeout; if the slave stretches longer than this, the transaction is aborted — requiring either a longer timeout configuration or polling-based retry instead of interrupt-driven reception.

Follow-up: How do you configure the I2C clock stretching timeout in STM32 HAL and what fault does it generate if exceeded?

Q6. What is I2C bus arbitration and when does it occur?

I2C bus arbitration occurs in multi-master systems when two masters simultaneously start a transaction; each master monitors SDA while transmitting, and if a master transmits 1 but reads 0 (the other master pulled SDA low), it loses arbitration, immediately stops, and retries later — the winning master never knows contention occurred. On a PCB with an STM32 application processor and a debug JTAG programmer both connected as I2C masters to the same RTC module, arbitration ensures correct operation even if both initiate simultaneously. Arbitration failure is detected in STM32 hardware via the ARLO (Arbitration Lost) flag in I2C_SR1 and triggers an I2C error interrupt.

Follow-up: What is the difference between I2C arbitration and SPI bus contention?

Q7. What are reserved I2C addresses and how do 10-bit addresses work?

Reserved 7-bit addresses include 0x00 (general call), 0x01–0x07 (reserved), 0x78–0x7F (10-bit address prefix) — devices must not use these as their own address. For 10-bit addressing, the master sends 0b11110XX followed by the two-byte address instead of the usual single 7-bit byte, allowing 1023 unique addresses. In practice, nearly all commercially available sensors use 7-bit addressing with 1–3 address bits configurable via address pins (e.g., BMP388 SDO pin selects 0x76 or 0x77) — 10-bit addressing is rarely encountered outside large industrial systems with many identical sensors.

Follow-up: What is the I2C general call address (0x00) and what is it used for?

Q8. How do you handle I2C bus lockup when a slave holds SDA low?

If a slave is holding SDA low (from a partial transaction interrupted by MCU reset or power glitch), the I2C bus is locked and no new transactions can start. Recovery is done by sending up to 9 manual clock pulses on SCL (while the slave is still asserting SDA) until the slave releases SDA, then issuing a STOP condition; most I2C slave devices release SDA within 9 additional clocks as they complete or abort the interrupted transaction. STM32 HAL_I2C_DeInit() followed by manually toggling PB6 (SCL) nine times as GPIO output, then reinitializing I2C, is the standard software recovery sequence in production firmware with a watchdog-triggered recovery path.

Follow-up: How do you prevent I2C bus lockup in a system with watchdog resets and multiple I2C slaves?

Q9. What is I2C fast-plus and high-speed mode and what do they require?

I2C Fast-Plus (FM+) operates at 1 MHz and requires open-drain drivers capable of sinking 20 mA (vs 3 mA in standard/fast mode) and pull-up resistors below 450 Ω; High-Speed mode (HS-mode) at 3.4 MHz uses a current-source pull-up switched in by a master code byte to achieve fast rise times, with bus capacitance limited to 100 pF. STM32F7 and H7 series I2C peripherals support FM+ at 1 MHz with internal 20 mA current drive; using standard 4.7 kΩ pull-ups at 1 MHz gives rise time of 4.7k × 50p = 235 ns — right at the 260 ns limit, so 2.2 kΩ is recommended for margin. In practice, most sensor-based embedded systems use 100–400 kHz and never need FM+ or HS mode.

Follow-up: What PCB constraints prevent the use of I2C HS-mode at 3.4 MHz in typical industrial PCB designs?

Q10. How do you multiplex multiple I2C buses or expand past 127 devices?

An I2C multiplexer IC such as the TCA9548A provides 8 software-selectable I2C channels from a single master, allowing the same sensor address to be used on each channel — solving address conflict when using 8 identical sensors. On an STM32 smart agriculture board with eight identical SHT30 sensors (all at address 0x44), a TCA9548A at address 0x70 selects each channel in turn; the master enables channel 0 by writing 0x01 to TCA9548A, reads SHT30, then switches to channel 1 by writing 0x02, and so on. Level-translating I2C expanders (PCA9306) allow mixing 1.8 V sensors on a 3.3 V master I2C bus using bidirectional MOSFET level translation.

Follow-up: What is an I2C level translator and when is it required?

Q11. How do you implement I2C in software (bit-bang) when no hardware peripheral is available?

Bit-bang I2C implements start, stop, send bit, and receive bit as GPIO operations: set SDA high then SCL high (start: SDA falls while SCL high); for each bit, set SDA to the bit value, pulse SCL high for tHigh (≥600 ns at 400 kHz), then low. On an STM32F1 where I2C1 pins are occupied by another function, bit-bang I2C on PB8/PB9 using DWT cycle counter delays achieves 200 kHz with ±5% accuracy — adequate for polling a BMP180 every 100 ms. Software I2C cannot support clock stretching (the master drives SCL and does not monitor it for slave pull-down) and struggles with accurate timing when interrupts are enabled, which is why hardware I2C is always preferred.

Follow-up: What timing constraints in I2C are most difficult to satisfy in a bit-bang implementation and why?

Q12. What is the I2C acknowledge polling technique for EEPROM?

After initiating a write to an I2C EEPROM (e.g., AT24C256), the device is busy writing the page for up to 5 ms and will NACK all incoming address bytes until complete; acknowledge polling sends repeated START + address bytes until the EEPROM responds with ACK, indicating the write cycle has finished. Without acknowledge polling, the firmware must insert a 5 ms delay after every write — using polling, the firmware retries every 100 µs and typically catches the EEPROM ready in 1–3 ms, improving write throughput by 2–4×. HAL_I2C_IsDeviceReady() in STM32 HAL implements acknowledge polling with a configurable retry count and timeout, wrapping this loop into one function call.

Follow-up: What is the page write size of AT24C256 EEPROM and what happens if you write across a page boundary?

Q13. How do you debug I2C communication problems using a logic analyzer?

Connecting a Saleae Logic 8 to SDA and SCL and enabling the I2C protocol decoder immediately shows every address, data byte, ACK/NACK, start, and stop in a readable annotation layer — the most common faults (NACK on address, missing ACK on data, short SDA to GND, stretched clock) are instantly visible without any calculation. If a BME280 NACK's the 7-bit address 0x76, the logic analyzer confirms whether the correct address byte (0xEC for write, 0xED for read) is being sent and whether the SDA line is actually reaching the sensor, pointing to either a wrong address in firmware or a PCB break in the trace. Checking rise time on SCL and SDA waveforms on the logic analyzer against the I2C spec (300 ns max at 400 kHz) immediately diagnoses pull-up resistor problems.

Follow-up: What does an I2C bus look like on a logic analyzer when the pull-up resistors are absent or too large?

Q14. What is the I2C general call and SMBus extension?

The I2C general call address (0x00, write) broadcasts to all devices on the bus simultaneously — devices that recognize general call acknowledge and execute the command; one application is resetting all I2C devices in a power-on sequence. SMBus (System Management Bus) is a subset of I2C at 10–100 kHz with additional protocol rules including mandatory timeouts, packet error checking (CRC-8), and a defined set of commands for power management ICs, battery chargers (BQ40Z80), and voltage regulators on server motherboards. SMBus devices (TI BQ25895 charger) often appear on embedded boards and can be communicated with using standard I2C as long as the timing and level requirements are met.

Follow-up: What is the SMBus ALERT signal and how is it used for device-initiated communication?

Q15. How does I2C address conflict occur and how do you resolve it in hardware?

Address conflict occurs when two identical sensors with fixed I2C addresses are placed on the same bus — two MPU-6050 IMUs both respond at 0x68 simultaneously, corrupting SDA with simultaneous active-low drive when the addresses match. Hardware resolution: many sensors have one or two address pins (AD0 on MPU-6050 selects 0x68 or 0x69), allowing up to 2 or 4 instances per bus; for more instances, a TCA9548A I2C mux places each sensor on an isolated sub-bus. Software address change via an I2C command is supported by some devices (e.g., PCA9685 PWM controller) but requires careful sequencing at power-up before the default address is used.

Follow-up: How would you connect four MPU-6050 sensors (two address pins available) on a single I2C bus?