How it works
The 8085 has five interrupt inputs in priority order: TRAP (highest, 0024H, non-maskable, edge and level triggered), RST 7.5 (003CH, maskable, edge triggered), RST 6.5 (0034H, maskable, level triggered), RST 5.5 (002CH, maskable, level triggered), and INTR (0038H via external RST n instruction or INTA acknowledge cycle, lowest priority). TRAP is always active; the others are masked by the Interrupt Enable flip-flop (EI/DI instructions) and individual masks controlled by the SIM instruction. The RIM instruction reads the current mask status and pending interrupt flags.
Key points to remember
Interrupt vector addresses: TRAP→0024H, RST 7.5→003CH, RST 6.5→0034H, RST 5.5→002CH, RST 0 through RST 7→0000H through 0038H (spaced 8 bytes). SIM instruction: bit 3 (MSE=1) enables mask setting; bits 0,1,2 mask RST 5.5, 6.5, 7.5 respectively. Bit 6 of SIM resets RST 7.5 latch. INTR requires an external 8259 PIC or RST n instruction on the data bus during the INTA machine cycle. The ISR must save all registers (PUSH AF, PUSH BC...), service the device, restore registers (POP), and end with EI followed by RET (or RETI for TRAP). Forgetting EI before RET prevents further interrupts.
Exam tip
The examiner always asks you to compare all five 8085 interrupt types in a table covering priority, vector address, trigger type, and maskability — memorise the vector addresses and trigger types because they appear directly in fill-in-the-blank questions.