How it works
The 8086 is a 16-bit processor with a 20-bit address bus (1 MB memory space = 2²⁰) and a 16-bit data bus. It is divided into two units: BIU (Bus Interface Unit) handles instruction fetching, address generation via segment registers, and bus control; EU (Execution Unit) decodes and executes instructions. Segment registers (CS, DS, SS, ES) are 16-bit; physical address = segment × 16 + offset (20-bit result). General-purpose registers: AX, BX, CX, DX (each 16-bit, split into AH/AL, BH/BL, CH/CL, DH/DL); index registers SI, DI; stack pointer SP; base pointer BP; instruction pointer IP; flag register.
Key points to remember
Physical address calculation: CS:IP generates code segment address = CS × 10H + IP. SS:SP gives stack address. Memory is organised in 16-byte segments (paragraphs); segments can overlap. Minimum mode (MN/MX pin = HIGH): 8086 generates its own control signals, simpler system. Maximum mode (MN/MX = LOW): 8288 Bus Controller generates MRDC, MWTC, IORC, IOWC signals; used with 8087 NDP coprocessor. The 8086 has 256 interrupt types with vectors stored in the lowest 1 KB of memory (0000H–03FFH), each vector being a 4-byte CS:IP pair. Clock frequency is 5 MHz for original 8086, 8 MHz for 8086-2, 10 MHz for 8086-4.
Exam tip
Every Anna University paper asks you to explain the segmented memory architecture and calculate a physical address from a given CS:IP pair — show the ×10H (left shift by 4 bits) step explicitly, then the 20-bit addition, because both steps must appear for full marks.