How it works
The R-2R ladder DAC uses only two resistor values regardless of the number of bits — R and 2R — making it far more accurate and practical than a binary-weighted resistor DAC where a 12-bit version would need resistors spanning a 2048:1 range. Each bit node contributes current proportional to its binary weight through Thevenin superposition. For the ADC0804 successive-approximation ADC with an 8-bit result and Vref/2 = 2.56V (full scale 5.12V), resolution is 5.12/256 = 20 mV per LSB; conversion time is about 100 µs with a 640 kHz clock.
Key points to remember
Resolution of an n-bit ADC is Vref / 2ⁿ; an 8-bit ADC with 5V reference resolves to 19.5 mV. Quantisation error is ±½ LSB, unavoidable in any ADC. The successive-approximation ADC takes exactly n clock cycles for n bits, making conversion time predictable — 8 clock cycles for ADC0804. Flash ADC uses 2ⁿ − 1 comparators for n bits and is the fastest type, converting in a single clock cycle at the cost of hardware complexity. The dual-slope ADC offers high noise immunity but is slow, making it suitable for multimeters rather than data acquisition systems running at 1 MHz sample rates.
Exam tip
Every Anna University paper asks you to calculate the output voltage of an R-2R DAC for a given binary input code — show each bit's contribution using superposition and confirm the final voltage against the LSB resolution.