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Short notes

Successive Approximation ADC Short Notes

The ADC0804, an 8-bit successive approximation ADC running at a 1.28 MHz clock with RC = 10 kΩ and CC = 150 pF, appears on countless microcontroller trainer boards in Indian engineering labs — and when the start-of-conversion pin is pulsed, the internal SAR register performs a binary search across all 256 possible codes in exactly 8 clock cycles (plus 1 or 2 overhead cycles) before asserting the end-of-conversion signal. This binary search strategy is why the SAR ADC needs exactly N clock cycles for N bits, making it far faster than a single-slope or dual-slope ADC while using far fewer comparators than a flash converter.

EEE, ECE, EI

How it works

The SAR (Successive Approximation Register) algorithm works as a binary search: set the MSB, compare DAC output to input voltage. If DAC output > Vin, clear the MSB; else keep it set. Repeat for each subsequent bit. After N steps, the N-bit digital code is locked. A DAC inside the ADC generates the trial voltage. For the ADC0804 with Vref/2 = 1.25 V (full-scale 2.5 V) and 8 bits, LSB = 2.5/256 ≈ 9.77 mV. Conversion time T_conv = N / f_clock; at 1.28 MHz clock, T_conv = 8/1.28 MHz ≈ 6.25 μs, giving a maximum sampling rate of about 160 kS/s. A sample-and-hold circuit is needed at the input to prevent the input signal from changing during the N-cycle conversion period.

Key points to remember

The SAR ADC requires exactly N clock cycles for N-bit resolution — this linear scaling is its main advantage over flash (2^N comparators) and integrating ADCs (very slow). Resolution is 1 LSB = Vref/2^N; for a 12-bit ADC with 5 V reference, 1 LSB = 1.22 mV. Quantisation error is ±½ LSB = ±0.61 mV in this case. The SAR ADC is monotonic, meaning its output always increases as input increases, because it uses an inherently monotonic R-2R or binary-weighted DAC. Flash ADCs are fastest (1 clock cycle, 2^N − 1 comparators) but power-hungry; sigma-delta ADCs are slowest but achieve 16–24 bit resolution for audio. SAR ADCs occupy the mid-range in speed and resolution (8–16 bits, up to ~5 MSPS) and are the workhorses of industrial measurement systems and MCU on-chip ADCs.

Exam tip

The examiner always asks you to trace through the SAR algorithm for a 4-bit ADC with Vref = 16 V and a given input voltage (e.g., 9.5 V) — show each bit decision in a table with columns: Bit, Trial Value, Compare Result, Register Value; this step-by-step table earns full marks.

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