How it works
In a ripple (asynchronous) counter, each flip-flop's Q output clocks the next stage — propagation delay accumulates across stages, so a 4-bit ripple counter built with 74LS76 flip-flops has a maximum cumulative delay of about 4 × 25 ns = 100 ns, limiting maximum clock frequency. Synchronous counters like the 74163 use a common clock to all flip-flops with combinational logic generating J and K inputs, so all outputs change within one propagation delay of the clock edge. The 74163 has synchronous load, synchronous clear, and a ripple-carry output (RCO) for cascading without extra glue logic.
Key points to remember
MOD-N counter design using the reset technique: for MOD-6, let the counter reach the count of 6 (0110), decode it with a NAND gate, and feed the output back to the asynchronous clear — the counter resets before the state is fully visible, so the sequence is 0 through 5. Synchronous reset gives a cleaner waveform. The 74163 is a 4-bit synchronous MOD-16 counter; cascading two gives MOD-256. Ripple counters consume less power but produce glitch outputs during transitions; synchronous counters are glitch-free but need more combinational logic. Maximum modulus of an n-bit counter is 2ⁿ.
Exam tip
The examiner always asks you to design a MOD-6 or MOD-10 counter using JK flip-flops with the full state diagram, next-state table, K-map simplification, and timing diagram — skip any of these steps and you lose partial marks.