How it works
The 74LS74 dual D flip-flop captures the D input on the rising edge of CLK and presents it at Q, where it stays locked regardless of subsequent D changes until the next active clock edge. The characteristic equation is simply Q(next) = D, which eliminates all forbidden or undefined states. Asynchronous preset (PRE-bar) and clear (CLR-bar) inputs override the clock entirely — pulling CLR-bar LOW forces Q LOW within about 25 ns regardless of CLK state. Setup time for 74LS74 is typically 20 ns and hold time is 5 ns; violating either causes the output to enter a metastable state.
Key points to remember
The D flip-flop is the only type where the next state equals the input directly: Q(next) = D. Converting a JK to D requires K = J-bar; converting T to D requires T = D XOR Q. Propagation delay from clock edge to output change in 74LS74 is about 25 ns maximum on a 5V supply. The setup time violation window creates metastability, where Q neither settles to 0 nor 1 for a statistically variable resolution time — this is an MTBF calculation topic in advanced papers. Shift registers, sequence detectors, and pipeline stages all use D flip-flops as their fundamental storage element.
Exam tip
Every Anna University paper has a question asking you to convert a D flip-flop into a JK or T flip-flop — derive the excitation equations and draw the logic diagram with external gates, not just the truth table.