How it works
A Xilinx 7-series FPGA is built from: CLBs (Configurable Logic Blocks), each containing two slices with four 6-input LUTs (Look-Up Tables) and eight D flip-flops. A 6-input LUT implements any Boolean function of 6 variables by storing 64 bits of truth table in SRAM. CLBs are arranged in a 2D array connected by a hierarchical routing fabric of wire segments and programmable interconnect points (PIPs). I/O Blocks (IOBs) at the periphery support LVCMOS, LVDS, and SSTL standards. Hard IP blocks include: BRAM (36 Kbit dual-port block RAM), DSP48E1, PCIe controller, GTP/GTX high-speed serial transceivers at up to 10 Gbps. FPGA configuration is loaded from an SPI flash on power-up into SRAM cells — the configuration is volatile and re-loaded every power cycle.
Key points to remember
SRAM-based FPGAs (Xilinx, Intel/Altera) are reprogrammable but volatile — configuration is lost at power-off. Antifuse FPGAs (Microsemi ProASIC) are one-time programmable but radiation-tolerant and secure, used in aerospace. Flash-based FPGAs retain configuration at power-off without an external flash. A 6-input LUT can implement any 6-variable function; cascading two 6-LUTs using carry logic implements a 7-variable function or a full adder with carry propagation. The routing delay in an FPGA typically exceeds the logic delay by 3–5× — most timing closure effort in FPGA design is routing, not logic. Partial reconfiguration allows a region of the FPGA to be reprogrammed while the rest continues operating, a feature used in adaptive signal processing and software-defined radio.
Exam tip
The examiner always asks you to draw the internal structure of a CLB showing LUT, flip-flop, and carry chain, and explain how a 6-input LUT implements any Boolean function — state that the 64-bit SRAM stores the complete truth table of the 6-variable function and the inputs select the appropriate bit as output.