How it works
A half adder adds two single bits A and B, producing Sum S = A⊕B (XOR) and Carry C = A·B (AND). It handles no carry input, limiting it to the least-significant bit position. A full adder adds A, B, and carry-in Cin, producing Sum S = A⊕B⊕Cin and Carry-out Cout = AB + Cin(A⊕B). The full adder requires two half adders and one OR gate: first HA gives S1 = A⊕B and C1 = AB; second HA gives S = S1⊕Cin and C2 = S1·Cin; final OR gives Cout = C1 + C2. Gate count: half adder needs 1 XOR + 1 AND = 2 gates. Full adder needs 2 XOR + 2 AND + 1 OR = 5 gates minimum, or can be built from 9 NAND gates. A 4-bit ripple carry adder chains four full adders; worst-case delay is 4 × (carry propagation delay per stage), limiting speed for wide adders.
Key points to remember
Half adder: S = A⊕B, C = AB; two gates. Full adder: S = A⊕B⊕Cin, Cout = AB + BCin + ACin = AB + Cin(A⊕B); five gates. The ripple carry adder propagates carry serially — for 16-bit addition, carry must ripple through 16 stages, making it slow. Carry lookahead adder (CLA) pre-computes carries in parallel using generate (G = AB) and propagate (P = A⊕B) signals: Cn+1 = Gn + Pn·Cn; the 74HC182 CLA unit implements this for 4-bit groups. Full adder can also perform subtraction: to subtract B from A, apply 2's complement of B (invert B bits and set Cin = 1) to the adder inputs. One full adder building block can be reused for both addition and subtraction with an XOR-controlled inversion gate on each B input.
Exam tip
The examiner always asks you to draw the full adder circuit using two half adders and derive the sum and carry expressions — write S = A⊕B⊕Cin and Cout = AB + Cin(A⊕B), then draw the gate diagram with both half adders labelled explicitly.