How it works
The JK flip-flop eliminates the forbidden state of the SR by feeding Q back to the J gate and Q-bar back to the K gate internally. The characteristic equation is Q(next) = J·Q-bar + K-bar·Q. When J=1 and K=0, the flip-flop sets; J=0 and K=1 resets it; J=K=1 toggles. The race-around condition occurs in level-triggered JK designs when J=K=1 and the clock remains HIGH for longer than the propagation delay — Q oscillates unpredictably. The master-slave configuration solves this by using two cascaded latches clocked on opposite phases.
Key points to remember
Race-around is specific to level-triggered JK flip-flops with J=K=1 and clock pulse width greater than the flip-flop's propagation delay. Master-slave JK flip-flops sample inputs on the clock's rising edge and update output on the falling edge, making them immune to race-around. The 7476 operates from a 5V supply with a maximum clock frequency of about 20 MHz. Converting JK to D flip-flop requires connecting K = J-bar, a standard exam conversion. Excitation table entries for J=K=X (don't care) occur during hold transitions, giving JK the simplest next-state design equations among all flip-flop types.
Exam tip
The examiner always asks you to explain race-around condition with a timing diagram and show how master-slave configuration eliminates it — draw both clocks (master and slave) clearly on the same timeline.