How it works
Moore FSM: output depends only on the current state. For a 1011 detector, typically 5 states are needed (S0 to S4). Output is registered and glitch-free because it changes only on clock edges. Mealy FSM: output depends on both current state and current input. For the same 1011 detector, only 4 states suffice — one fewer than Moore — because part of the output logic is absorbed into the transition arcs. The state transition table for a Mealy machine has columns: Present State, Input, Next State, Output. For Moore: Present State, Next State per input, Output (column per state). In an ASM (Algorithmic State Machine) chart, Moore outputs appear in the state box; Mealy outputs appear in the decision diamond's conditional output box.
Key points to remember
Mealy machines generally require fewer states than Moore machines for the same function — for a pattern detector with N-bit pattern, Mealy needs N states versus N+1 for Moore. Moore machine outputs are synchronous and less susceptible to glitches; Mealy outputs can glitch if the input changes between clock edges. Both models are equivalent in computational power — any Moore machine can be converted to Mealy and vice versa. The number of flip-flops required is ⌈log₂(number of states)⌉; for 4 states, 2 flip-flops; for 5 states, 3 flip-flops — this affects hardware cost. In VHDL/Verilog synthesis, separating the next-state logic, output logic, and register update into three always/process blocks is the recommended coding style for both FSM types.
Exam tip
The examiner always asks you to draw the state diagram for a sequence detector (commonly 1011 or 0101) in both Mealy and Moore models, compare the number of states, and write the state transition table — draw both diagrams side by side and explicitly count and compare states.