How it works
A PLL has three core blocks: a Phase Detector (PD) that produces a voltage proportional to the phase difference between input and VCO output, a Low-Pass Filter (LPF) that smooths the PD output to remove double-frequency components, and a Voltage Controlled Oscillator (VCO) whose free-running frequency f0 shifts by KVCO·Vc Hz/V. The LPF time constant determines capture transient response. Lock range (hold-in range) ΔfL = ±(KD·KVCO·A) rad/s, where KD is phase detector gain and A is open-loop gain; the LM565 has a lock range of ±60% around f0. Capture range is always smaller than lock range and depends on LPF bandwidth.
Key points to remember
Capture range is always less than or equal to lock range — this inequality is a favourite 2-mark question. Lock range depends on loop gain, while capture range depends on both loop gain and LPF bandwidth. For the LM565 with a 5 V supply, the VCO free-running frequency is set by an external RC: f0 = 1.2/(4·R·C). The phase detector in a basic PLL is an analog multiplier or XOR gate; the output contains a DC term proportional to phase error plus a double-frequency term removed by the LPF. Second-order PLLs with an active loop filter achieve zero steady-state phase error for a step frequency input — an important performance distinction from first-order PLLs.
Exam tip
The examiner always asks you to draw the complete PLL block diagram, label KD, KVCO, and the LPF, and then explain the difference between capture range and lock range — most students lose marks by reversing which is larger.