How it works
Sinusoidal PWM (SPWM): triangular carrier at fc (typically 2–20 kHz) compared with sinusoidal reference at f1 (fundamental, e.g. 50 Hz). Frequency modulation ratio mf = fc/f1; amplitude modulation ratio ma = Vref_peak/Vcarrier_peak. For ma ≤ 1 (linear range), output fundamental Vout = ma × Vdc/2. Space Vector PWM (SVPWM) treats the three-phase output as a single rotating vector in αβ space — it achieves 15% higher bus utilisation than SPWM (maximum Vout = Vdc/√3 vs Vdc/2) and produces lower THD. Hysteresis current control switches at variable frequency, keeping actual current within a ±ΔI band around the reference sine wave.
Key points to remember
Selected Harmonic Elimination (SHE): switching angles are pre-calculated offline to eliminate specific low-order harmonics (typically 5th and 7th). For a single-phase inverter with two notches per quarter-cycle, two angles α1 and α2 can eliminate two harmonics. SHE produces lower switching losses than SPWM because switching frequency is lower, but requires ROM lookup tables. Naturally sampled SPWM uses the instantaneous intersection of reference and carrier; regularly sampled SPWM samples the reference at carrier peaks/troughs — simpler to implement in DSP (e.g. TMS320F28335). Dead-band compensation corrects the voltage error introduced by IGBT dead time, which becomes significant at low modulation indices.
Exam tip
The examiner always asks you to compare SPWM and SVPWM — the key points are bus voltage utilisation (SVPWM achieves 15.5% more), THD, and implementation complexity on a DSP or FPGA.