How it works
With S1=0, S0=1 on the 74194, the register shifts right — data enters at the serial-right input (SR) and each clock edge moves every bit one position toward QD. Parallel load (S1=1, S0=1) transfers all four D inputs to Q outputs in a single clock cycle. For left shift (S1=1, S0=0), data enters at the serial-left input (SL). The maximum clock frequency for 74194 is about 36 MHz on a 5V supply, making it fast enough for most parallel-to-serial conversion tasks up to several megahertz.
Key points to remember
Four operating modes of 74194: S1S0=00 is hold, 01 is shift right, 10 is shift left, 11 is parallel load. A ring counter is a shift register with QD connected back to the serial input — for a 4-bit ring counter, only one bit is HIGH and it circulates, giving 4 distinct states. A Johnson counter (twisted ring) feeds Q-bar of the last stage back to the input, producing 2n states for n flip-flops — an 8-state sequence from 4 flip-flops. Serial-in serial-out (SISO) mode produces a delay equal to n clock periods, useful as a digital delay line at 1 MHz clock rates.
Exam tip
The examiner always asks you to draw the state sequence and timing diagram for a 4-bit Johnson counter built from 74194 — remember it has 8 states and the waveforms are phase-shifted replicas of the clock.