How it works
In a NAND-based SR latch, both S-bar and R-bar are active-low. Pulling S-bar LOW sets Q HIGH regardless of the previous state; pulling R-bar LOW resets Q to LOW. When both inputs are HIGH, the latch holds its previous state — that's the memory behaviour. The forbidden condition occurs when both S-bar and R-bar are pulled LOW simultaneously, forcing both Q and Q-bar HIGH and violating the complementary output rule. On release, the final state becomes unpredictable, depending on gate propagation delays in the nanosecond range.
Key points to remember
The SR flip-flop characteristic equation is Q(next) = S + R-bar·Q, valid only when S·R = 0. For a NOR-based latch, inputs are active-high and the forbidden state is S=1, R=1. Clock edge-triggering eliminates the transparency problem of level-sensitive latches, confining state changes to the rising or falling edge. Setup time for a standard 74LS74 is 20 ns before the clock edge; violating this causes metastability. The excitation table of the SR flip-flop — showing required S and R for each Q to Q(next) transition — is a mandatory derivation in sequential circuit design problems.
Exam tip
The examiner always asks you to derive the characteristic equation and draw the excitation table of the SR flip-flop, so memorise that S·R = 0 is the constraint and know what happens when it's violated.