How it works
Standard TTL (74xx) uses bipolar transistors with a totem-pole output stage; the output HIGH voltage is typically 2.4V minimum and output LOW is 0.4V maximum on a 5V supply. CMOS (4000 series at 5V) has output HIGH near VDD (4.95V) and output LOW near 0V, giving much wider noise margins: HIGH noise margin is about 1.45V for CMOS versus only 0.4V for TTL. Fan-out of 74LS logic is 20 standard LS loads. Propagation delay of 74LS is about 10 ns, while 4000-series CMOS runs 50–100 ns at 5V but improves to under 10 ns for 74HC series at higher supply voltages.
Key points to remember
74LS TTL operates only at 5V ± 5%; CMOS 4000-series works from 3V to 18V. Fan-out for standard TTL is 10, for 74LS it is 20. Power dissipation of CMOS is nearly zero at DC but rises linearly with frequency (P = C·V²·f), reaching parity with TTL at about 1 MHz for 4000-series. To interface TTL driving CMOS at 5V, a 10 kΩ pull-up resistor on the TTL output raises the HIGH level above the CMOS threshold of 3.5V. The 74HC and 74HCT families are CMOS speed-compatible with TTL voltage levels, making them the standard choice for modern mixed-logic designs.
Exam tip
The examiner always asks you to compare TTL and CMOS on fan-out, noise margin, propagation delay, and power dissipation in a table — memorise the 74LS and 4000-series numbers exactly as they appear in your textbook.