Interview questions & answers
Q1. What is a DC-DC converter and what are the basic topologies?
A DC-DC converter is a switched-mode power supply that transfers energy from an input DC voltage to a different output DC voltage using switches, inductors, and capacitors without significant power loss. The basic non-isolated topologies are buck (step-down), boost (step-up), and buck-boost (inverting), while isolated topologies include flyback, forward, push-pull, half-bridge, and full-bridge. A TPS54360 buck converter from Texas Instruments operating at 400 kHz converts 12 V to 3.3 V at 3.5 A on a PCB area smaller than 1 cm², illustrating why switching converters have replaced linear regulators in portable electronics.
Follow-up: What are the main advantages of a switching converter over a linear regulator like LM317?
Q2. Derive the voltage conversion ratio of a buck converter in CCM.
In steady state CCM, the volt-second balance on the inductor requires VL_on × D × T = VL_off × (1-D) × T; since VL_on = Vin - Vout and VL_off = Vout, this gives (Vin - Vout) × D = Vout × (1-D), simplifying to Vout/Vin = D (duty cycle). For a 12 V to 3.3 V buck converter, D = 3.3/12 = 0.275, meaning the switch is on for 27.5% of each switching period. The linear relationship between Vout and D makes the buck converter straightforward to control with a simple PWM feedback loop and is why it dominates in CPU core voltage regulators.
Follow-up: How does the conversion ratio change if the converter operates in discontinuous conduction mode (DCM)?
Q3. Derive the voltage conversion ratio of a boost converter in CCM.
Applying volt-second balance to the boost converter inductor: VL_on × D × T = VL_off × (1-D) × T; since VL_on = Vin and VL_off = Vin - Vout, the balance gives Vin × D = (Vout - Vin) × (1-D), yielding Vout/Vin = 1/(1-D). For a 5 V input boosted to 12 V, D = 1 - 5/12 = 0.583, meaning the switch is on for 58.3% of the period. The 1/(1-D) relationship shows that output voltage approaches infinity as D approaches unity, which in practice means light-load regulation at high duty cycle is difficult and DCM is preferred for wide load ranges.
Follow-up: Why is the boost converter non-minimum phase and what does it mean for control design?
Q4. How do you calculate the minimum inductance for CCM operation of a buck converter?
The critical inductance for CCM at minimum load current Io_min is Lmin = (Vin - Vout) × D / (2 × fsw × Io_min). For a 12 V to 3.3 V buck at 400 kHz with minimum load 0.5 A: Lmin = (12 - 3.3) × 0.275 / (2 × 400k × 0.5) = 2.39/400k = 5.97 µH; choosing 10 µH keeps the converter well in CCM at half load. Operating in CCM gives predictable small-signal behavior and simpler control, which is why switching to DCM at light load is handled by pulse-skipping modes in ICs like TPS62130 rather than by reducing L.
Follow-up: What changes in the converter behavior when it crosses from CCM into DCM as load decreases?
Q5. What is the buck-boost converter and what is its output voltage polarity?
A buck-boost converter produces a negative output voltage (inverted polarity relative to input ground) with magnitude that can be either less than or greater than the input voltage, with Vout/Vin = -D/(1-D). A buck-boost with Vin = 5 V and D = 0.5 gives Vout = -5 V, and at D = 0.75 gives Vout = -15 V — the same circuit covers both step-up and step-down with a single topology. The inverted polarity makes it directly useful for generating -5 V or -12 V rails from a single positive supply in op-amp circuits, audio amplifiers, and sensor signal conditioning.
Follow-up: What is the SEPIC converter and how does it achieve non-inverting buck-boost operation?
Q6. What is the difference between CCM and DCM in a switching converter?
In CCM (Continuous Conduction Mode), inductor current never reaches zero between switching cycles, giving lower peak current, lower RMS current, and better EMI behavior; in DCM (Discontinuous Conduction Mode), inductor current reaches zero during each off period, giving higher peak current and a different, simpler small-signal transfer function. A TPS5430 buck converter operating at full load (3 A) is in CCM; as load drops below the critical boundary current (about 0.5 A), it enters DCM. Most modern controllers use CCM at full load for efficiency and DCM or pulse-skip at light load for quiescent current reduction.
Follow-up: What is the boundary conduction mode and what advantages does it offer in PFC circuits?
Q7. How does the output capacitor selection affect the transient response of a buck converter?
During a load step, the output voltage sag is initially dominated by the ESR of the output capacitor and then by its capacitance: ΔV_ESR = ΔI × ESR and ΔV_C = ΔI × ΔT / C. For a CPU VRM delivering a 20 A load step with a 470 µF polymer capacitor (ESR = 5 mΩ), the initial ESR drop is 100 mV and the subsequent droop depends on the control loop bandwidth. Using multiple low-ESR SP-Cap or MLCC capacitors in parallel reduces the initial transient sag, which is why modern VRMs use ten to twenty 47 µF MLCCs rather than a single large electrolytic.
Follow-up: What is the relationship between control loop bandwidth and output capacitor size in a voltage regulator?
Q8. What is a flyback converter and when is isolation required?
A flyback converter is an isolated buck-boost where energy is stored in the coupled inductor (transformer) during the on-time and transferred to the secondary during the off-time, providing galvanic isolation between input and output with turns ratio adjustable gain. A 5 W USB charger like the one in a Redmi phone uses a flyback converter at 100–130 kHz with a PC40 ferrite EE16 core to produce 5 V/1 A from 90–265 V AC after the bridge rectifier. Isolation is required by IEC 62368-1 safety standards whenever the output is touched by a user and the input is connected to mains, or when noise isolation between subsystems is needed.
Follow-up: What is the voltage spike on the primary switch of a flyback converter and how is it clamped?
Q9. What is synchronous rectification and why is it used in low-voltage buck converters?
Synchronous rectification replaces the catch diode in a buck converter with a low RDSon MOSFET that is switched complementarily to the main switch, reducing the diode forward drop from 0.4–0.7 V to RDSon × IL — typically 10–30 mV at rated current. An AON6954 MOSFET with RDSon = 2.1 mΩ at 3.3 V VGS carrying 5 A has a conduction drop of only 10.5 mV, versus 500 mV for a Schottky diode — improving efficiency from about 88% to 94% at that operating point. At sub-1 V output voltages for modern SoC power rails, the diode drop would represent 50–70% of the output voltage, making synchronous rectification not just beneficial but essential.
Follow-up: What is body diode conduction and dead time in a synchronous buck converter, and how does it affect efficiency?
Q10. What is volt-second balance and charge balance in switching converter analysis?
Volt-second balance states that the average voltage across an inductor must be zero in steady state, since any net average voltage would cause the current to ramp to infinity; charge balance states that the average current into a capacitor must be zero in steady state. These two principles are the foundation for deriving conversion ratios and component equations for any switching topology without solving differential equations. Applying volt-second balance to a Cuk converter's two inductors simultaneously gives both the input and output conversion ratio as Vout/Vin = -D/(1-D), identical to a buck-boost but with non-pulsating input and output currents.
Follow-up: Apply volt-second balance to derive the conversion ratio of the SEPIC converter.
Q11. What is the role of the error amplifier and compensation network in a PWM controller?
The error amplifier compares the feedback voltage (output sampled through a resistor divider) to a reference voltage and produces an error signal that, after compensation filtering, sets the PWM duty cycle to regulate the output. A Type III compensation network in a UC3842-controlled flyback provides sufficient phase boost (>45° phase margin) across the crossover frequency of 5–20 kHz to ensure stable closed-loop operation. Without compensation, the LC output filter of a buck converter creates a double pole at its resonant frequency that causes 180° phase shift and zero gain margin, leading to oscillation.
Follow-up: What is the crossover frequency and phase margin of a converter control loop, and what values are considered acceptable?
Q12. How does the switching frequency affect converter size, efficiency, and EMI?
Higher switching frequency reduces the required inductance and capacitance (and therefore physical size) because energy stored per cycle is smaller, but increases switching losses in the MOSFETs and core losses in the inductor, reducing efficiency at high load. A LMR33630 buck converter at 400 kHz uses a 3.3 µH inductor and 22 µF output capacitor; the same converter at 2.2 MHz needs only a 0.47 µH inductor and 10 µF but runs 3–5% hotter at full load. EMI worsens at higher frequency in the frequency band where the switching harmonics land, requiring more aggressive filtering and careful PCB layout.
Follow-up: What is spread-spectrum frequency dithering in a switching converter and why is it used?
Q13. What is the input capacitor in a buck converter used for and how is it sized?
The input capacitor supplies the pulsating input current drawn by the buck converter's switch during the on-time, preventing large voltage ripple on the input supply rail and reducing conducted EMI. For a 12 V to 5 V, 3 A buck at 400 kHz with D = 0.417, the input RMS ripple current is approximately 0.5 × ΔIL ≈ 0.3 A RMS, requiring a capacitor rated for this ripple current — typically a 47 µF X7R ceramic with 5 A ripple rating placed within 5 mm of the switch node. Using a bulk electrolytic alone at the input creates a high-frequency resonance with PCB trace inductance that can cause conducted EMI failures in FCC/CE testing.
Follow-up: Why is the ceramic capacitor placed close to the switch and the bulk electrolytic placed further away?
Q14. What is a multi-phase buck converter and where is it used?
A multi-phase (interleaved) buck converter uses N parallel channels phase-shifted by 360°/N, so their inductor current ripples partially cancel, reducing input and output capacitor ripple current by a factor proportional to N at the expense of N times the inductors. Intel VR13 and VR14 CPU voltage regulator modules use 4–8 phase interleaved bucks to supply 100–200 A at 0.8–1.0 V to core processors while achieving output voltage transient response within 100 mV for 100 A load steps. Each phase inductor can be small (100–220 nH) because the combined effective ripple frequency is N × fsw, dramatically shrinking the output capacitor bank.
Follow-up: How does current sharing between phases work in a multi-phase buck converter?
Q15. What is the difference between voltage mode and current mode control in a DC-DC converter?
Voltage mode control uses only the output voltage error to set duty cycle through a single feedback loop, requiring careful compensation for the double LC pole; current mode control adds an inner current loop that senses inductor current cycle-by-cycle, making the inductor appear as a controlled current source and simplifying outer voltage loop compensation to a single pole system. A UCC28C44 current mode flyback controller with a simple RC compensation achieves stable regulation, whereas a voltage mode flyback requires Type III compensation for similar bandwidth. Current mode control also provides inherent cycle-by-cycle current limiting and easier paralleling of converter modules.
Follow-up: What is sub-harmonic instability in peak current mode control and how is slope compensation used to prevent it?
Common misconceptions
Misconception: The duty cycle of a buck converter can be set above 1 (100%) to get output higher than input.
Correct: In a buck converter, duty cycle is bounded between 0 and 1 by definition; output voltage is always lower than or equal to input voltage, and a boost or flyback topology must be used to step up voltage.
Misconception: CCM is always more efficient than DCM for a given converter.
Correct: DCM has higher peak currents and RMS losses but eliminates reverse recovery loss in the catch diode and simplifies control; at light loads, a converter purposely entering DCM or pulse-skip mode can be more efficient than forcing CCM with a minimum load.
Misconception: A larger output capacitor always improves transient response.
Correct: Transient response is limited by the control loop bandwidth; a larger capacitor increases the LC time constant and requires a lower loop crossover frequency to maintain stability, which can actually worsen load transient response.
Misconception: The flyback converter's transformer stores no energy, like a signal transformer.
Correct: A flyback transformer is actually a coupled inductor that stores energy in its core air gap during the primary on-time and releases it to the secondary during the off-time — this is fundamentally different from a forward converter transformer that transfers energy simultaneously.