Inverter Interview Questions

Q1. What is an inverter and how does it differ from a rectifier?

An inverter converts DC power to AC power using controlled switches (IGBTs or MOSFETs) fired in a sequence that synthesizes the desired AC waveform, while a rectifier converts AC to DC. A Fronius Symo 10 kW grid-tie solar inverter converts 600–800 V DC from a PV string to 400 V, 50 Hz three-phase AC using a full-bridge IGBT inverter stage. Unlike a rectifier, an inverter must generate its own frequency reference and voltage waveform, making it far more complex in its control system.

Follow-up: What is the difference between a grid-connected and a stand-alone inverter in terms of control?

Q2. What is the difference between a Voltage Source Inverter (VSI) and a Current Source Inverter (CSI)?

A VSI has a stiff DC voltage source (capacitor) at its input and controls output voltage waveform, while a CSI has a stiff DC current source (large inductor) at its input and controls output current waveform. An ABB ACS880 VFD uses a diode rectifier + capacitor bank (VSI) to drive induction motors; CSI drives use thyristors and are still used in very large LCI (load-commutated inverter) compressor drives above 10 MW. VSI dominates modern drives because IGBTs are inherently voltage-controlled switches and capacitor DC links are more practical than large inductors at medium power levels.

Follow-up: What type of load is most naturally suited for a CSI and why?

Q3. Explain single-phase half-bridge and full-bridge inverter operation.

A half-bridge inverter uses two switches and a split DC bus (two equal capacitors), producing ±Vdc/2 at the output — a 48 V DC bus gives ±24 V AC peak, useful in low-power UPS and audio amplifiers. A full-bridge uses four switches in H-bridge configuration, producing ±Vdc — a 400 V DC bus gives ±400 V AC peak — doubling the output voltage capability for the same DC bus, which is why grid-tied single-phase PV inverters use full-bridge with 350–400 V DC link. Full-bridge also allows bipolar PWM for better harmonic performance, whereas half-bridge output has only three levels.

Follow-up: What is unipolar PWM in a single-phase full-bridge inverter and how does it improve harmonic performance?

Q4. What is sinusoidal PWM (SPWM) and how does it synthesize a sine wave?

SPWM compares a sinusoidal modulating signal at the desired output frequency against a high-frequency triangular carrier wave; a switch is turned on when the sine exceeds the triangle and off otherwise, producing a series of variable-width pulses whose average value tracks the sine wave. A 2-level SPWM inverter at 400 V DC with 10 kHz carrier produces output voltage harmonics at 10 kHz ± 2 × 50 Hz sidebands, which are easily filtered by the motor leakage inductance. The modulation index M = Vm_sine / Vm_carrier determines the fundamental output voltage: Vfundamental = M × Vdc/2, allowing smooth voltage control from 0 to 100%.

Follow-up: What is the third harmonic injection PWM and how does it increase the maximum linear modulation range?

Q5. What is the modulation index in an inverter and what happens at overmodulation?

Modulation index M is the ratio of the peak of the reference sinusoid to the peak of the triangular carrier (M = Vm_ref / Vm_carrier); at M = 1, the inverter is at the boundary of linear modulation. For M > 1 (overmodulation), the reference exceeds the carrier for part of each cycle, causing the pulse pattern to approach a square wave and introducing low-order odd harmonics (3rd, 5th, 7th). In a VFD like a Danfoss FC302, overmodulation is avoided during V/Hz operation to keep motor harmonic heating within design limits; however, square wave operation (M >> 1) at full speed is used to maximize fundamental voltage from the available DC bus.

Follow-up: Why does a square wave output give maximum fundamental voltage from a given DC bus in an inverter?

Q6. Explain space vector PWM (SVPWM) and its advantages over SPWM.

SVPWM represents the three-phase inverter output as a voltage vector in a two-dimensional αβ plane and synthesizes the reference vector by time-averaging two adjacent active vectors and a zero vector, achieving 15.5% higher DC bus utilization than SPWM without entering overmodulation. In a TMS320F28379D-based VFD, the SVPWM algorithm computes sector, dwell times, and switch sequence every 50 µs, producing balanced three-phase output with lower switching losses than carrier-based methods. The centered placement of zero vectors (V0 and V7) in SVPWM minimizes switching transitions per cycle and reduces inverter harmonic distortion compared to SPWM at the same carrier frequency.

Follow-up: How are the six active vectors and two zero vectors of a 2-level 3-phase inverter defined?

Q7. What are dead time and dead time compensation in an inverter?

Dead time is a deliberate delay inserted between turning off one switch and turning on the complementary switch in the same inverter leg, preventing a shoot-through short circuit across the DC bus. In a 600 V, 10 kHz IGBT inverter, dead time is typically 2–4 µs; this causes the output voltage fundamental to be reduced and distorted, introducing low-order voltage harmonics proportional to dead time × switching frequency × Vdc. Dead time compensation algorithms in DSP controllers detect current direction and add or subtract a correction to the duty cycle each switching period, recovering the lost voltage and reducing torque ripple at low speeds in servo drives.

Follow-up: What is the effect of dead time on low-speed torque control performance in a servo drive?

Q8. What are the main harmonic reduction techniques in inverters?

Harmonic reduction techniques include increased pulse number (12-pulse or 18-pulse through phase-shifted transformers), selective harmonic elimination (SHE) PWM that pre-calculates switching angles to cancel specific harmonics, output LC filters, active front-end rectifiers with current control, and multi-level inverter topologies. A 12-pulse inverter using two 6-pulse bridges with a delta-delta and delta-star supply transformer eliminates the 5th and 7th harmonics from the input, reducing total harmonic distortion from ~25% to below 12%. Multi-level neutral-point-clamped (NPC) inverters used in ABB ACS2000 medium-voltage drives produce so many voltage steps that motor current is nearly sinusoidal without any additional filter.

Follow-up: How does a 3-level NPC inverter reduce harmonic distortion compared to a 2-level inverter?

Q9. What is a neutral-point-clamped (NPC) inverter?

A 3-level NPC inverter has three output voltage levels (+Vdc/2, 0, -Vdc/2) per phase by using four switches per leg and two clamping diodes that connect the midpoint to the split DC bus capacitor neutral point, reducing the dv/dt and harmonic content compared to a 2-level inverter with the same switch voltage rating. An ABB ACS800-17 at 3.3 kV medium voltage uses a 3-level NPC stage with 1700 V IGBTs instead of 3300 V devices, reducing switching losses and the need for dv/dt filters at the motor terminals. NPC is the standard topology for medium-voltage drives between 2.3 kV and 6.6 kV because it halves the switch voltage stress per level.

Follow-up: What is the neutral point voltage balancing problem in a 3-level NPC inverter?

Q10. How does a grid-tied solar inverter synchronize to the grid?

A grid-tied inverter uses a Phase-Locked Loop (PLL) algorithm running on the DSP to track the grid voltage angle in real time, then controls the output current to be in phase with the grid voltage for unity power factor real power injection. A SMA Sunny Boy 5 kW inverter running a synchronous reference frame PLL on a TMS320F28035 achieves phase lock within 200 ms of grid connection and maintains synchronism during ±10% voltage and ±2 Hz frequency variations. Grid codes in India (CEA regulations 2019) require anti-islanding protection — active frequency or impedance injection — to detect loss of grid and trip the inverter within 2 seconds.

Follow-up: What is anti-islanding protection and why is it mandatory for grid-tied inverters in India?

Q11. What is MPPT in a solar inverter and which algorithms are commonly used?

Maximum Power Point Tracking (MPPT) is a real-time algorithm that continuously adjusts the PV array operating voltage to the point of maximum power output on the P-V curve, compensating for changes in irradiance and temperature. The Perturb and Observe (P&O) algorithm, used in most string inverters including Fronius and SMA models, steps the reference voltage up or down every 50–100 ms and observes whether power increases or decreases to converge on the MPP. Incremental Conductance is preferred in rapidly varying irradiance (cloudy days) because it can determine the MPP direction analytically rather than by trial-and-error perturbation.

Follow-up: What is partial shading in a PV array and how does it create multiple peaks on the P-V curve?

Q12. What is the difference between V/Hz control and vector control of an induction motor using an inverter?

V/Hz (scalar) control maintains a constant ratio of stator voltage to frequency, providing approximate flux control adequate for fans and pumps, but gives slow and imprecise torque response due to no decoupled flux and torque control. Field-Oriented Control (FOC) vector control, used in ABB ACS880 drives, transforms stator currents into a rotating reference frame aligned with rotor flux, allowing independent and instantaneous control of flux-producing and torque-producing current components like a DC machine. A servo drive using FOC on a 400 W PMSM can achieve torque response faster than 1 ms, which is impossible with V/Hz control regardless of switching frequency.

Follow-up: What is the difference between direct FOC and indirect FOC for induction motor control?

Q13. What is shoot-through in a half-bridge inverter leg and how is it prevented?

Shoot-through occurs when both the high-side and low-side switches of the same inverter leg conduct simultaneously, placing a direct short circuit across the DC bus, causing catastrophic overcurrent and device destruction in microseconds. In a 400 V DC bus IGBT inverter, a shoot-through event can discharge the DC bus capacitor at rates exceeding 1000 A/µs; the IGBT gate driver IC (e.g., IXYS DESAT protection in IR2110) detects desaturation (rising VCE) and shuts off the gate within 2–3 µs. Hardware dead time plus software interlock plus gate driver desaturation protection are all three needed because any single protection can fail to operate in time for high-speed faults.

Follow-up: What is the minimum dead time required for a 600 V IGBT with a turn-off time of 200 ns, and what margin should be added?

Q14. What is the output filter design for a grid-tied inverter?

A grid-tied inverter output filter attenuates switching harmonics below limits set by IEEE 1547 or Indian grid code; an LCL filter (two inductors with a shunt capacitor) provides 60 dB/decade attenuation above resonance and achieves smaller inductors than a simple L filter for the same harmonic rejection at 10–16 kHz switching frequency. For a 10 kW, 400 V, 16 kHz inverter, a typical LCL filter uses Li = 0.3 mH (inverter side), Cf = 10 µF, Lg = 0.15 mH (grid side), placing resonance at about 3.6 kHz — well below switching frequency. Active damping of the LCL resonance via software is preferred over passive damping resistors to avoid additional loss in the capacitor branch.

Follow-up: What is the stability problem associated with LCL filter resonance in grid-tied inverters?

Q15. How does a UPS inverter differ from a VFD inverter?

A UPS inverter must generate a stable sinusoidal voltage with very low THD (<3%) under varying non-linear loads (computers, servers) and must transfer seamlessly between inverter and bypass in less than 4 ms, whereas a VFD inverter controls motor current and can tolerate more output distortion. An Eaton 9PX 10 kVA online UPS uses a full-bridge IGBT inverter with a 20 kHz carrier and an LC output filter sized to give <2% THD into a crest-factor 3 load, maintaining output regulation within ±1% from no load to full load. VFDs do not need sub-millisecond bypass transfer and can distort voltage waveform because induction motor leakage inductance naturally attenuates harmonics.

Follow-up: What is the crest factor of a load and why does it matter for UPS inverter design?