PWM Interview Questions

Q1. What is PWM and what does duty cycle mean?

PWM (Pulse Width Modulation) is a technique of switching a digital signal on and off at a fixed frequency while varying the on-time (pulse width) to control the average value of the output. Duty cycle D = ton / T × 100%, so a 5 V signal at 50% duty cycle on a 10 kHz PWM delivers an average of 2.5 V to a filter. PWM is used for everything from dimming an LED on an STM32 GPIO to controlling the switching transistor in a 1 kW buck converter, making it one of the most universally applied concepts in electronics.

Follow-up: What is the relationship between PWM duty cycle and average output voltage when a low-pass filter is applied?

Q2. How is PWM generated using a microcontroller timer?

A microcontroller timer in PWM mode counts up to a period register (ARR) and compares the count to a capture/compare register (CCR); output goes high when count < CCR and low otherwise, producing a PWM signal with frequency = f_clk / (prescaler × ARR) and duty cycle = CCR/ARR. On an STM32F103 with 72 MHz clock, setting prescaler = 0, ARR = 719, CCR = 360 gives 100 kHz PWM at 50% duty cycle on TIM2_CH1. The hardware timer runs independently of the CPU, so once configured, the PWM continues without CPU intervention — a crucial property for real-time control loops.

Follow-up: What is center-aligned PWM mode and why is it used in motor control?

Q3. What is the resolution of a PWM signal and how does it relate to timer bit width?

PWM resolution is the minimum duty cycle step size, given by 1/ARR × 100% for a given period — a 16-bit timer with ARR = 65535 gives 0.0015% resolution, while an 8-bit timer with ARR = 255 gives only 0.39%. An STM32G474 timer running at 170 MHz with a 12-bit resolution PWM (ARR = 4095) at ~41.5 kHz gives 4096 distinct duty cycle steps — adequate for audio class-D amplifiers and motor current control. Increasing resolution requires either reducing frequency or using a higher-frequency timer clock, and the two requirements trade off against each other.

Follow-up: What is the maximum achievable PWM frequency for a 10-bit resolution on a 72 MHz microcontroller clock?

Q4. What is the difference between edge-aligned and center-aligned PWM?

Edge-aligned PWM counts from 0 to ARR (up-counting) and the pulse starts at the beginning of each period; center-aligned (up-down) counts from 0 to ARR and back, centering the pulse symmetrically around the period midpoint. In a 3-phase motor drive, center-aligned PWM on TIM1 of an STM32 ensures that all three-phase switching events are symmetric around the timer center, which is when the ADC trigger is placed for noise-free current sampling at the midpoint of zero vectors. Center-aligned mode also halves the effective ripple frequency perceived by the motor, reducing core losses at the same switching frequency.

Follow-up: What is the ADC injection trigger method in STM32 motor control and how does center-aligned PWM facilitate it?

Q5. How is three-phase complementary PWM generated for a motor drive?

A three-phase complementary PWM module (e.g., TIM1 on STM32 or ePWM on TMS320F28035) generates six PWM signals — three for the high-side and three complementary for the low-side IGBTs — with programmable dead time inserted between complementary signals. On a TMS320F28379D, the ePWM module generates six 20 kHz signals with 2 µs dead time and distributes them to six gate driver ICs (e.g., Si8233) driving a 3-phase full-bridge IGBT module. The dead time register in hardware ensures sub-clock-cycle accuracy in dead-time insertion, unlike software-managed delays that are subject to interrupt latency jitter.

Follow-up: What is the consequence of incorrect dead time in a three-phase motor drive — what fault occurs and how is it detected?

Q6. What is the switching frequency in a PWM converter and how do you select it?

Switching frequency is the repetition rate of the PWM cycle; selecting it involves trading off switching losses (which increase with frequency) against passive component size (which decreases with frequency) and control bandwidth (which increases with frequency). A 10 kW motor drive at 10 kHz switching frequency uses 300 µH inductors and achieves 3 kHz current control bandwidth; at 20 kHz, inductors shrink to 150 µH and bandwidth can reach 6 kHz, but IGBT switching losses double. Texas Instruments application note SLVA386 recommends 1/10th of switching frequency as maximum achievable current loop bandwidth, which guides the frequency selection for a target control response.

Follow-up: Why are switching frequencies of 8–16 kHz particularly common in motor drives?

Q7. What is DPWM (Discontinuous PWM) and how does it reduce inverter switching losses?

Discontinuous PWM clamps one phase to the positive or negative DC rail for 60° per fundamental cycle — the phase whose current is largest — eliminating switching of that phase leg during its clamped interval and reducing total inverter switching losses by about 33%. In an ABB or Schneider VFD at high output frequency, DPWM120 (clamping for 120° per cycle) reduces IGBT switching losses by 33% compared to SVPWM with no noticeable increase in output THD for three-phase induction motor loads. The tradeoff is slightly higher current ripple during the clamped intervals and need for slightly larger output inductors or capacitors to maintain the same THD specification.

Follow-up: What are the different variants of DPWM (DPWM0, DPWM1, DPWM2, DPWM3) and how do they differ?

Q8. How does PWM frequency affect EMI and what methods reduce EMI from PWM circuits?

PWM switching generates broadband EMI due to fast voltage transitions (dv/dt); the fundamental switching frequency and its harmonics cause conducted and radiated EMI peaks in the spectrum from 150 kHz to 30 MHz covered by CISPR 32 and FCC Part 15 testing. A 400 kHz buck converter with a 1 ns rise time MOSFET gate drive generates significant harmonics up to 100 MHz; using a 10 Ω gate resistor to slow rise time to 10 ns reduces high-frequency EMI by 20 dB at the cost of slightly higher switching losses. Spread-spectrum frequency dithering — sweeping frequency ±5% of nominal — spreads spectral energy into the noise floor, reducing peak EMI by 10–12 dBµV in certification testing without any hardware filter change.

Follow-up: What is the relationship between MOSFET gate resistance, rise time, and EMI spectral content?

Q9. What is soft switching in a PWM converter and how is it achieved?

Soft switching — Zero Voltage Switching (ZVS) or Zero Current Switching (ZCS) — turns the switch on or off when the voltage across it or the current through it is zero, eliminating the CV²f switching energy loss that dominates at high frequency. A LLC resonant converter (used in server power supplies like the Delta DPS-1600) achieves ZVS of the primary MOSFETs by using the resonant inductor and capacitor to ensure the MOSFET body diode conducts before the gate is driven, so turn-on occurs at zero drain-source voltage. ZVS allows LLC converters to operate efficiently at 500 kHz–1 MHz, achieving 96–98% efficiency in data center PSUs — unachievable with hard switching at those frequencies.

Follow-up: What is the difference between ZVS and ZCS and which one reduces turn-on or turn-off losses?

Q10. How is PWM used for DC motor speed control?

PWM controls DC motor speed by varying the average voltage applied to the motor armature — at 50% duty cycle with a 24 V supply, the average terminal voltage is 12 V, producing approximately half the full-load speed. An L298N H-bridge IC driven by an STM32 with 20 kHz PWM and 30% duty cycle gives 7.2 V average to a 12 V gear motor, and increasing duty cycle from 30% to 80% smoothly accelerates the motor without the resistive losses of a rheostat. PWM frequency must be above the motor electrical time constant corner frequency (typically 500 Hz to 2 kHz for small motors) to keep current ripple below 10% of rated current and prevent jerky rotation.

Follow-up: What is the back-EMF of a DC motor and how does it affect current at different duty cycles?

Q11. What is dead-band compensation in a three-phase PWM inverter?

Dead-band compensation corrects the output voltage error introduced by dead time by adding or subtracting a correction term to the duty cycle command based on the sign of the phase current each PWM cycle, restoring the average voltage to the commanded value. In a PMSM servo drive at 5% speed (low frequency), the dead-time voltage error at 10 kHz with 3 µs dead time is about 3 µs/100 µs × 600 V = 18 V — large enough to cause significant torque ripple without compensation. Texas Instruments C2000 motor control SDK implements dead-band compensation in the CMPS module of the ePWM peripheral, reducing sixth-order torque ripple by 70–80% in servo applications.

Follow-up: Why does dead-time distortion cause sixth-harmonic torque ripple in a three-phase motor drive?

Q12. What is the ripple current in the output inductor of a buck converter and how is it related to PWM frequency?

Inductor ripple current ΔiL = (Vin - Vout) × D / (L × fsw); doubling the switching frequency halves the ripple current for the same inductance, or allows the inductance to be halved for the same ripple. A 12 V to 5 V, 5 A buck with L = 22 µH at 300 kHz has ΔiL = (12-5) × 0.417 / (22µH × 300k) = 0.44 A peak-to-peak — about 8.8% of rated current, well within the 20–30% design guideline. Reducing L to 11 µH at 600 kHz maintains the same ripple while halving inductor physical size — a classic design tradeoff exploited by GaN converter designs operating above 1 MHz.

Follow-up: What is the relationship between inductor ripple current and the output capacitor ripple voltage?

Q13. What is oversampling and averaging in PWM-based ADC readings?

Oversampling involves sampling the ADC multiple times per PWM period and averaging the results to improve effective resolution beyond the hardware ADC bit count — averaging 4 samples improves resolution by 1 bit (6 dB SNR gain). An STM32F3 with a 12-bit ADC oversampled 16× during center-aligned PWM zero vectors achieves 14-bit effective resolution for motor current measurement without adding external hardware. This technique is standard in FOC implementations where DC bus current shunt sensing must resolve small differential currents to accurately reconstruct phase currents.

Follow-up: What is the difference between oversampling for noise reduction and oversampling for resolution improvement?

Q14. What is PWM rectifier (active front end) and how does it improve power quality?

A PWM rectifier (active front end, AFE) replaces the diode bridge with a bidirectional IGBT bridge operated with current-controlled PWM, drawing nearly sinusoidal current from the AC supply at unity power factor and enabling regeneration back to the grid. A Siemens SINAMICS S120 active line module at 132 kW draws grid current with THD below 5% and unity power factor at all loads, complying with IEEE 519 harmonic limits without passive harmonic filters. The AFE also provides ride-through capability by controlling DC bus voltage during supply dips, unlike a passive diode rectifier where DC bus follows the supply.

Follow-up: What is the control architecture of a PWM rectifier and how does it maintain DC bus voltage regulation?

Q15. How does PWM dithering work and why is it used in precision analog applications?

PWM dithering adds a small high-frequency noise signal to the PWM duty cycle command before truncation to the timer resolution, spreading quantization error across frequency and improving the effective resolution of the PWM DAC function at frequencies below the dither frequency. In a precision current source controlled by a 10-bit PWM on a Cortex-M4, dithering at 1/16 LSB amplitude allows 14-bit effective resolution in the DC output after the output LC filter, enabling finer control of a laser diode drive current. Without dithering, the current would step in discrete jumps of 1 LSB = 1/1024 of full scale, causing visible intensity steps in a laser optical output.

Follow-up: How does dithering differ from noise shaping in a delta-sigma modulator?