Interview questions

Embedded Communication Protocols Interview Questions

Embedded communication protocols are among the most frequently tested topics in technical interviews across both core embedded companies like Bosch, L&T, and Texas Instruments, and IT companies like TCS, Infosys, and Wipro for IoT and embedded profiles. ECE and EI students must prepare this thoroughly. These questions appear consistently in the first and second technical rounds and often include both theory and debugging scenarios.

ECE, EI

Interview questions & answers

Q1. Explain the I2C protocol. How does it handle multiple devices on the same bus?

I2C (Inter-Integrated Circuit) is a two-wire (SDA, SCL), synchronous, half-duplex serial protocol supporting multiple masters and up to 127 devices (7-bit addressing) on the same bus, with each transaction starting with a START condition, 7-bit address, R/W bit, and ACK. The MPU-6050 IMU communicates at 400 kHz Fast Mode over I2C, and selecting between two devices on the same bus (e.g., two BMP280 sensors) uses the AD0 pin to set the LSB of the 7-bit address. The protocol uses open-drain bus lines with pull-up resistors so any device can pull the line low without bus contention — this is the key reason it supports multi-master operation.

Follow-up: What happens on the I2C bus when two masters attempt to transmit simultaneously?

Q2. What are the main differences between I2C and SPI protocols?

SPI uses four wires (MOSI, MISO, SCLK, CS), is full-duplex, has no addressing (uses dedicated chip-select per slave), and runs at 10–100 MHz, while I2C uses two wires, is half-duplex, addresses slaves over the bus, and runs at 100 kHz to 3.4 MHz. The MPU-9250 IMU supports both protocols; SPI at 1 MHz is preferred for high-speed DMA transfers in real-time attitude control, while I2C is used when pin count is limited on a small PCB. SPI wastes a GPIO pin per additional slave, while I2C grows the slave count without extra pins but is slower and more protocol-overhead-heavy.

Follow-up: When would you choose I2C over SPI despite its lower speed?

Q3. Describe the UART protocol. What is a baud rate and how do you select it?

UART (Universal Asynchronous Receiver-Transmitter) is an asynchronous serial protocol using two wires (TX, RX) with a start bit, 5–9 data bits, optional parity, and one or two stop bits, with no clock signal — both sides must be pre-configured to the same baud rate. A GPS module like u-blox NEO-M8N communicates at 9600 baud by default, sending 10 bits per character (1 start + 8 data + 1 stop) to give a throughput of 960 bytes/second. Baud rate is selected based on the acceptable bit error rate given the clock accuracy; mismatches of more than 3–5% between the two UARTs cause framing errors.

Follow-up: What is the purpose of the parity bit in UART and what types are available?

Q4. What is the CAN bus protocol and why is it used in automotive systems?

CAN (Controller Area Network) is a differential, multi-master serial bus using two wires (CAN_H, CAN_L) with CSMA/CD+AMP arbitration, message-based communication (11 or 29-bit IDs), and hardware CRC error detection, designed for real-time control in noisy environments. In a car, ECUs for ABS (Bosch ABS ECU), engine management, and body control all share a single 500 kbit/s CAN bus, reducing the wire harness from hundreds of point-to-point wires to a single twisted pair. CAN's non-destructive bitwise arbitration ensures that the highest-priority message (lowest ID) wins the bus without data loss, making it deterministic for safety-critical systems.

Follow-up: How does CAN arbitration work and what determines message priority?

Q5. What is the difference between RS-232 and RS-485?

RS-232 is a single-ended, point-to-point standard using ±12 V logic levels for one transmitter and one receiver, while RS-485 is a differential, multi-drop standard using ±200 mV common-mode range supporting up to 32 unit loads (effectively 32 devices) on a single bus at up to 10 Mbit/s. An industrial PLC communicating with 16 temperature controllers on a factory floor uses RS-485 at 115200 baud in a half-duplex 2-wire configuration, which would be impossible with RS-232. RS-485's differential signaling rejects common-mode noise up to ±7 V, making it suitable for cable runs over 1000 m in electrically noisy environments.

Follow-up: Why are termination resistors required at both ends of an RS-485 bus?

Q6. Explain the SPI protocol in detail, including clock polarity and phase (CPOL and CPHA).

SPI transfers data synchronously by shifting bits on the MOSI/MISO lines on either the rising or falling edge of SCLK, with CPOL defining the idle state of the clock (0 = idle low, 1 = idle high) and CPHA defining whether data is sampled on the first (0) or second (1) edge, giving four modes (0,0), (0,1), (1,0), (1,1). The BME280 sensor uses SPI Mode 0 (CPOL=0, CPHA=0) — data is clocked on the rising edge with clock idle-low. Mismatching SPI mode between the MCU and sensor is one of the most common debugging issues and causes the first byte to be received correctly but subsequent bytes to be shifted.

Follow-up: How do you verify the SPI mode required by a sensor datasheet when the bus is not responding?

Q7. What is I2C clock stretching and when does a slave device use it?

Clock stretching is when an I2C slave pulls the SCL line low after a byte to insert a wait state, signaling the master to pause until the slave is ready to proceed, used when the slave needs time to process data (e.g., an ADC completing a conversion). The ADS1115 16-bit ADC stretches the clock between the register address byte and the data byte while the ADC conversion completes, requiring the master I2C driver to support clock stretching or the read will return stale data. Some fast MCU I2C controllers (STM32 in certain hardware modes) do not correctly handle clock stretching and must be configured carefully.

Follow-up: What happens if an I2C master does not support clock stretching but the slave requires it?

Q8. What is the USB protocol and how does it differ from UART in terms of architecture?

USB (Universal Serial Bus) is a host-centric, differential serial bus with a strictly hierarchical topology (one host, tree of hubs and devices), using NRZI encoding, packet-based transactions, and enumeration where devices announce their class and capabilities, unlike UART's simple point-to-point connection. An STM32F4 microcontroller acting as a USB CDC (Communications Device Class) device appears as a virtual COM port to the PC and transfers data at 12 Mbit/s (Full Speed), far exceeding UART's typical 921600 baud. USB's enumeration, endpoint, and descriptor system adds significant protocol complexity compared to UART but enables plug-and-play device detection and class-based drivers.

Follow-up: What is USB enumeration and what information does a device provide to the host during enumeration?

Q9. What is the I2C start and stop condition, and why are they significant?

A START condition is a high-to-low transition on SDA while SCL is high, and a STOP condition is a low-to-high transition on SDA while SCL is high; these are the only times SDA changes while SCL is high, since during data transfer SDA must be stable when SCL is high. A REPEATED START (Sr) allows a master to change direction (write address then read data) without releasing the bus, used when reading from a specific register of a sensor like the BMP280 where you must first write the register address. Failure to correctly generate START and STOP conditions is the most common cause of I2C bus hangs in firmware.

Follow-up: What causes an I2C bus to get stuck in a locked state and how do you recover it?

Q10. What is the difference between synchronous and asynchronous serial communication?

Synchronous communication uses a shared clock signal (SCL in I2C, SCLK in SPI) so the transmitter and receiver are always aligned, while asynchronous communication (UART) has no clock and relies on pre-agreed baud rates with start and stop bits to frame each character. SPI at 40 MHz can transfer a 4-byte register in 800 ns, while UART at 115200 baud takes 347 μs for the same 4 bytes — a 435× speed difference. The overhead of synchronous protocols is the extra clock wire, while asynchronous protocols sacrifice speed for simplicity and work well for slow peripheral communication like GPS or GSM modules.

Follow-up: What is the maximum distance for reliable SPI communication and what limits it?

Q11. How does CAN handle error detection and what are the error states of a CAN node?

CAN uses five error mechanisms: CRC check, bit stuffing check, frame check, bit monitoring (transmitter reads back its own bit), and ACK check; any detected error causes the node to transmit an error frame and increment its transmit (TEC) or receive (REC) error counter. A node transitions from Error Active (TEC/REC < 128) to Error Passive (TEC/REC 128–255) and finally to Bus Off (TEC > 255), where it disconnects from the bus and can only re-join after 128 × 11 recessive bits. This graduated fault confinement prevents a single faulty ECU — such as a water-damaged wheel speed sensor node — from permanently crashing the entire vehicle CAN network.

Follow-up: What is bit stuffing in CAN and why is it used?

Q12. What is MODBUS protocol and in what industrial applications is it used?

MODBUS is a simple master-slave application-layer protocol originally designed by Modicon for PLCs, using RTU (binary over RS-485) or TCP (over Ethernet) framing to read and write registers (holding registers, coils, input registers) on field devices. An ABB variable frequency drive uses MODBUS RTU over RS-485 at 19200 baud to receive speed setpoint commands and report current, voltage, and fault status to a SCADA system. MODBUS is the most widely deployed industrial protocol because it is royalty-free, simple to implement, and supported by virtually all PLCs, sensors, and drives from Siemens, Schneider, and ABB.

Follow-up: What is the difference between MODBUS RTU and MODBUS ASCII framing?

Q13. Explain the concept of DMA (Direct Memory Access) and its importance in embedded serial communication.

DMA allows a peripheral like a UART or SPI controller to transfer data directly to/from memory without CPU intervention, freeing the processor to execute other tasks during the transfer. An STM32F7 MCU uses DMA to receive 4096 bytes from a SPI flash memory (W25Q128) in the background while the CPU processes previously received data, achieving near-continuous throughput without polling or interrupt overhead. Without DMA, a high-baud UART receiving 1 Mbit/s data would require an interrupt every 10 μs, consuming over 50% of a 100 MHz CPU's cycles just in interrupt overhead.

Follow-up: What is a DMA circular buffer and how is it used for continuous UART reception?

Q14. What is the difference between half-duplex and full-duplex communication, and give a protocol example of each?

Full-duplex allows simultaneous bidirectional transmission on separate physical channels, while half-duplex allows bidirectional transmission but only one direction at a time on a shared channel. SPI is full-duplex — MOSI and MISO are separate lines and both shift simultaneously on every clock cycle. I2C and RS-485 are half-duplex — SDA in I2C is shared for both directions and RS-485 requires direction control (DE/RE pins) to switch between transmit and receive. UART is technically full-duplex when both TX and RX lines are used, but many embedded applications use only one direction, making it effectively simplex.

Follow-up: What is the role of the DE (Driver Enable) pin in an RS-485 transceiver like the MAX485?

Q15. What is the LIN bus protocol and how does it differ from CAN?

LIN (Local Interconnect Network) is a single-wire, low-speed (up to 20 kbit/s), master-only-initiation serial bus used for low-priority body electronics like window motors, seat position, and mirror adjustment, while CAN is a high-speed, multi-master, differential bus for real-time control. In a car, the body control module (BCM) communicates with door window actuators and courtesy lighting over a LIN cluster at 10 kbit/s, while the ABS and engine ECUs use a 500 kbit/s CAN bus. LIN requires only a single wire plus ground and uses the supply voltage for logic levels, reducing the cost of body electronics networking where CAN's speed and error robustness are unnecessary.

Follow-up: What is the LIN break field and how does the master node use it to synchronize slave nodes?

Common misconceptions

Misconception: I2C ACK means the data was processed successfully by the slave.

Correct: I2C ACK only confirms that the slave received the byte and is ready for the next one; it does not indicate the data was valid or acted upon correctly.

Misconception: UART baud rate and bit rate are always different values.

Correct: For UART, baud rate and bit rate are numerically equal since each symbol encodes exactly one bit; baud rate and bit rate differ only in multi-level encoding schemes.

Misconception: SPI is always faster than I2C for any given clock frequency.

Correct: SPI is faster in data throughput but uses more pins; for short transactions, I2C's overhead is manageable, and at 3.4 MHz High-Speed mode I2C is sufficient for most sensor applications.

Misconception: CAN bus can have an unlimited number of nodes.

Correct: Standard CAN supports up to 110 nodes limited by bus electrical loading, and each node adds capacitance that reduces the maximum achievable bit rate.

Quick one-liners

How many wires does I2C use?Two — SDA (data) and SCL (clock), both open-drain with pull-up resistors.
What is the maximum standard I2C bus speed?3.4 MHz in High-Speed mode, with Fast-Mode Plus at 1 MHz and standard mode at 100 kHz.
What is the idle state of a UART line?Logic high (mark state) — the line sits at the high voltage level between transmissions.
What does MOSI stand for in SPI?Master Out Slave In — the data line driven by the master and read by the slave.
What type of encoding does CAN use on the bus?NRZ (Non-Return-to-Zero) with bit stuffing to ensure transitions for clock synchronization.
What is the voltage swing for RS-485 differential signaling?A differential voltage of at least ±200 mV between the A and B lines is required to distinguish logic levels.
What is a UART framing error?An error condition where the stop bit is not detected at the expected time, usually caused by a baud rate mismatch between transmitter and receiver.
What is clock polarity (CPOL) in SPI?CPOL defines the idle state of the clock line — CPOL=0 means idle low, CPOL=1 means idle high.
What is the dominant bit in CAN bus logic?Logic 0 (dominant) overrides logic 1 (recessive) on the CAN bus, enabling non-destructive bitwise arbitration.
What is the purpose of a pull-up resistor on the I2C bus?It holds SDA and SCL high when no device is pulling them low, enabling the open-drain wired-AND bus operation required for multi-master and clock stretching.

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