Interview questions & answers
Q1. What is a JFET and how does it control current?
A JFET (Junction Field-Effect Transistor) is a voltage-controlled current device where the channel current between drain and source is controlled by reverse-biasing the gate-channel P-N junction, which widens the depletion region and narrows the conductive channel. In an N-channel JFET like 2N5457, applying Vgs = -2V reverse biases the gate junction, depleting the N-channel from the sides and reducing drain current from Idss ≈ 5 mA to about 1.5 mA. Because the gate is always reverse biased, gate current is only the reverse junction leakage (< 1 nA), giving the JFET an extremely high input impedance — a key advantage over BJT.
Follow-up: What is the difference between an N-channel and P-channel JFET in terms of biasing polarity?
Q2. What is Idss and Vp (pinch-off voltage) in a JFET and how do they characterize the device?
Idss is the drain-source saturation current when Vgs = 0V (gate shorted to source), and Vp (pinch-off voltage, also called Vgs(off)) is the gate-source voltage that reduces drain current to essentially zero by completely depleting the channel. For a 2N5484, Idss ranges from 1–5 mA and Vp from -0.3V to -3V — these are the two most important parameters for biasing design. Drain current in the saturation region follows Id = Idss × (1 - Vgs/Vp)², so a 2N5484 with Idss=3 mA and Vp=-3V at Vgs=-1.5V gives Id = 3×(1-(-1.5/-3))² = 3×0.25 = 0.75 mA.
Follow-up: Why does Idss vary widely between JFETs of the same part number?
Q3. What are the three operating regions of a JFET and what characterizes each?
The ohmic (linear) region has Vds < |Vgs - Vp| and the JFET behaves as a voltage-variable resistor; the saturation region has Vds > |Vgs - Vp| where Id is controlled only by Vgs and is nearly constant; and the cutoff region has |Vgs| ≥ |Vp| where Id ≈ 0. In an audio preamplifier using 2N5457, the JFET must be biased in the saturation region (Vds > 3V typically) for linear amplification; in an analog multiplexer or attenuator application, the ohmic region is used where the JFET acts as a voltage-controlled resistor with resistance ranging from 50 Ω (Vgs=0) to several MΩ (Vgs near Vp). Accidentally biasing in the ohmic region for amplification causes severe distortion.
Follow-up: What limits drain current in the saturation region of a JFET?
Q4. What is the transconductance (gm) of a JFET and how does it determine amplifier gain?
Transconductance gm = ΔId/ΔVgs at constant Vds, measured in millisiemens (mS), represents how much drain current changes per volt of gate-source signal. For the 2N5457 at bias point Id=1 mA, gm ≈ 2 mS from the datasheet; in a common-source amplifier with a 4.7 kΩ drain resistor, voltage gain Av = -gm × Rd = -2 mS × 4.7 kΩ = -9.4. JFET gm is typically 1–10 mS, much lower than BJT transconductance (gm = Ic/0.026 ≈ 40 mS at Ic=1 mA), which is why JFET amplifiers achieve lower voltage gain than equivalent BJT stages.
Follow-up: How does gm relate to Idss and Vp in the JFET square-law model?
Q5. What is self-bias in JFET and how is it the most common biasing method?
Self-bias uses a source resistor Rs to automatically establish the correct reverse Vgs: as Id flows through Rs, it creates a voltage drop Vs = Id×Rs that reverse biases the gate (held at ground through Rg) relative to source. For a 2N5459 with Idss=9 mA and Vp=-8V, to bias at Id=2 mA: Vgs = Vp×(1-√(Id/Idss)) = -8×(1-√(2/9)) = -8×(1-0.47) = -4.2V, so Rs = Vgs/Id = 4.2/0.002 = 2.1 kΩ → use 2.2 kΩ standard. Self-bias is preferred over voltage-divider bias because it automatically compensates for the wide Idss spread between individual JFETs of the same type number.
Follow-up: What is voltage-divider bias for JFET and why is it less common than self-bias?
Q6. What is the input impedance of a JFET and why is it higher than a BJT?
The JFET gate is always reverse biased, so gate current is only the junction reverse saturation current — typically 1 pA to 1 nA at room temperature — giving an input resistance of 10⁹ to 10¹² Ω. A 2N5457 has gate leakage Igs(max) = 1 nA at Vgs = -15V, giving Rin > 10¹⁴ Ω at typical operating voltages. This is why JFETs are used as the input stage of precision electrometer op-amps (like LF356, TL071) for measuring picoampere-level currents from pH sensors, ionization chambers, and charge amplifiers where BJT base current of 10–100 nA would be an unacceptable input error current.
Follow-up: What happens to gate leakage current as temperature increases in a JFET?
Q7. What is the common-source JFET amplifier and what are its gain and impedance characteristics?
A common-source JFET amplifier has the gate as input, drain as output, and source as common terminal; it provides voltage gain Av = -gm×Rd/(1+gm×Rs) if the source resistor is not bypassed, or Av = -gm×Rd with a bypass capacitor across Rs. With 2N5457 (gm=2 mS, Rd=10kΩ, Rs=1kΩ unbypassed): Av = -2×10/(1+2×1) = -6.7. Input impedance is essentially Rg (typically 1–10 MΩ) since gate current is negligible; output impedance is approximately Rd in parallel with 1/gm ≈ Rd for Rd >> 1/gm.
Follow-up: What is the common-drain (source follower) JFET configuration and what gain does it provide?
Q8. How does a JFET compare to a MOSFET and when would you choose a JFET?
A JFET uses a reverse-biased P-N junction to control the channel, requiring the gate to be reverse biased (negative for N-channel); a MOSFET uses an insulated oxide gate and can be both enhancement and depletion type, with essentially infinite input impedance for DC. JFETs are chosen over MOSFETs in analog front-ends where low noise is critical — the 2N5484 has noise voltage of 4 nV/√Hz versus 10–20 nV/√Hz for typical signal MOSFETs — because the JFET gate-channel junction noise (1/f corner around 10–100 Hz) is lower than MOSFET oxide interface traps (1/f corner up to 10 kHz). MOSFETs completely dominate digital circuits and power electronics; JFETs survive only in precision analog niches.
Follow-up: What is 1/f (flicker) noise and which device — JFET or MOSFET — has a lower 1/f corner frequency?
Q9. What is the pinch-off voltage and how is the JFET still useful above pinch-off?
Pinch-off voltage Vp is the gate voltage at which the drain current drops to near zero, but above pinch-off the JFET enters saturation — at Vds = Vgs - Vp the channel at the drain end just pinches but current still flows, controlled by Vgs. Confusingly, pinch-off refers to two different phenomena: the gate voltage Vgs(off) that cuts off the channel, and the Vds value at which the channel begins to saturate. At Vgs=0 and Vds = |Vp| = 3V for a 2N5457, the device is at the boundary of ohmic and saturation — increasing Vds further does not increase Id because the depletion pinch-point at the drain moves to accommodate increased field without increasing current.
Follow-up: What is channel length modulation in a JFET and how does it create a finite output impedance?
Q10. What is a current source using a JFET and how do you build a simple two-terminal constant current diode?
A two-terminal JFET current source (also called a current-limiting diode or CLD) connects gate to source (Vgs=0) and uses the device's self-limiting Idss as a fixed current; the J507 packaged JFET current limiter provides 4.7 mA ±30% from 1.5V to 100V, acting as a high-impedance constant current source. In a simple LED constant-current driver without a control IC, a single 2N5457 with gate shorted to source in series with the LED provides Idss ≈ 5 mA across supply voltages of 3V to 12V — maintaining constant LED brightness regardless of supply variation. The current accuracy of this circuit is limited by Idss spread (typically ±2× between individual JFETs) but is sufficient for indicator LEDs where brightness variation is acceptable.
Follow-up: How do you set a precise current value other than Idss using a JFET with a source resistor?
Q11. What is the noise advantage of JFETs in audio preamplifier design?
JFETs exhibit lower input voltage noise (en = 4–6 nV/√Hz) and especially lower 1/f noise corner frequency (10–100 Hz) compared to BJTs (which have lower en but significant base current noise for high source impedance) and MOSFETs (higher 1/f corner). The 2SK170 (now Toshiba discontinued) became legendary in audio for its en=0.9 nV/√Hz — it was used in the input stage of high-end microphone preamplifiers and studio mixing consoles. At source impedances above 1 kΩ, JFET input stages outperform BJT because JFET gate current noise is negligible while BJT base current noise (In = √(2qIb)) becomes significant.
Follow-up: What is the optimal source impedance for minimizing noise figure in a BJT versus JFET input stage?
Q12. What is the JFET small-signal model and what are its parameters?
The JFET small-signal model consists of a voltage-controlled current source gm×vgs representing the transconductance, a drain-source resistance rds representing channel-length modulation, and the three inter-terminal capacitances Cgs, Cgd, Cds. For the 2N5457 at Id=1 mA: gm ≈ 2 mS, rds ≈ 40 kΩ, Cgs ≈ 4.5 pF, Cgd ≈ 1.5 pF — these values are used to predict high-frequency gain rolloff and input capacitance. The Miller-multiplied Cgd is the dominant bandwidth-limiting capacitor in a common-source amplifier: effective input C = Cgd×(1+gm×Rd) = 1.5 pF × (1+2×10) = 31.5 pF, which with a 1 MΩ source resistance gives -3 dB at 5 kHz.
Follow-up: How does the Miller effect limit JFET amplifier bandwidth, and how do you reduce it?
Q13. What is the temperature coefficient of Idss in a JFET and where is it zero?
JFET Idss has a negative temperature coefficient above a certain bias point (typically at 60–70% of Idss) and positive below it, meaning there exists a specific drain current at which the temperature coefficient is zero — called the zero temperature coefficient (ZTC) point. At this ZTC point, usually around Id ≈ Idss/3 for many JFETs, the decrease in mobility with temperature exactly cancels the decrease in pinch-off voltage with temperature, making Id virtually temperature-independent. Biasing a 2N5457 at Id ≈ 1.5 mA (= Idss/3 ≈ 5/3 mA) in a temperature-stable gain stage exploits this ZTC point to achieve <0.1% Id variation over 0–70°C.
Follow-up: What causes the negative temperature coefficient of drain current in JFETs at high current?
Q14. What is a differential pair using JFETs and what is its advantage in precision instrument design?
A JFET differential pair uses two matched JFETs sharing a common source tail current, amplifying the difference between two input signals while rejecting common-mode voltages; the high input impedance and low gate current make it ideal for electrometers and instrumentation amplifier front ends. The LF412 op-amp uses a JFET differential input stage with matched 2N5459-type JFETs achieving Ibias < 50 pA — critical for integrating circuits with 100 MΩ feedback resistors where BJT base current would cause DC offset of 100 mV. Matching of Idss between the two JFETs is critical — a 5% Idss mismatch causes an input offset voltage of roughly 5% × Vgs_bias, which is why matched JFET pairs (like the SSM2210) are sold for precision differential applications.
Follow-up: What is common-mode rejection ratio (CMRR) of a JFET differential pair and what circuit element most affects it?
Q15. What is the on-resistance of a JFET in the ohmic region and how is it used in analog switching?
In the ohmic region, the JFET behaves as a resistor Rds(on) = 1/(gm0 × (1 - Vgs/Vp)) where gm0 is transconductance at Vgs=0; for a 2N5457 at Vgs=0, Rds(on) ≈ 200–600 Ω depending on the sample. Analog switches like the DG303 use P-channel and N-channel JFETs to route signals with Rds(on) below 300 Ω, enabling multiplexing of audio signals from multiple sensors to a single ADC. The Ron × Coff time constant of a JFET switch limits its bandwidth: a 300 Ω on-resistance with 5 pF off-capacitance gives a bandwidth of 1/(2π × 300 × 5pF) ≈ 106 MHz, adequate for audio but insufficient for RF signal switching where GaAs MESFET switches are preferred.
Follow-up: What is charge injection in a JFET analog switch and how does it cause errors in sample-and-hold circuits?
Common misconceptions
Misconception: A JFET is turned on by applying a positive voltage to the gate of an N-channel device.
Correct: An N-channel JFET is fully on at Vgs=0 (depletion-mode device); the gate must be made negative relative to source to reduce current, and positive bias would forward-bias the gate junction and allow gate current to flow.
Misconception: Pinch-off in a JFET means the device is turned off.
Correct: Pinch-off at a specific Vds value transitions the device from ohmic to saturation region where current is still flowing but is now controlled by Vgs — it does not mean zero current; cutoff occurs at Vgs = Vp.
Misconception: JFETs and MOSFETs have similar input impedance because both are FETs.
Correct: Both have very high input impedance for AC signals, but JFET DC gate leakage is 1 pA–1 nA while MOSFET gate leakage through the oxide can be sub-femtoampere or can be higher in nanometer nodes due to oxide tunneling — the comparison is technology-specific.
Misconception: A higher Idss JFET always provides higher amplifier gain.
Correct: Gain Av = -gm×Rd depends on transconductance gm, which is gm = 2Idss/|Vp| at Vgs=0, so higher Idss with proportionally higher |Vp| may give the same gm and identical gain.