Power MOSFET and IGBT Interview Questions

Q1. What is the fundamental structural difference between a Power MOSFET and an IGBT?

A Power MOSFET is a unipolar majority-carrier device (electrons in N-channel) with a DMOS structure; an IGBT (Insulated Gate Bipolar Transistor) adds a P+ substrate beneath the MOSFET structure, creating a PNP BJT that injects minority carriers (holes) into the N-drift region for conductivity modulation. The IGBT's conductivity modulation allows a 600V IGBT to carry 50A with an on-state voltage of about 2V, while a comparable power MOSFET would require a very large die to achieve similar Rdson and still show 5–10V drop at 50A. The minority carrier injection also causes the IGBT's characteristic tail current during turn-off, which is absent in the MOSFET.

Follow-up: What is conductivity modulation and why does it benefit high-voltage devices?

Q2. What is Rds(on) in a Power MOSFET and how does it depend on voltage rating?

Rds(on) is the drain-source on-resistance when the MOSFET is fully enhanced, and it determines conduction losses as P = I²×Rds(on). Rds(on) scales approximately as V_BR^2.5 for planar DMOS and V_BR^2.7 for superjunction MOSFETs — a 600V MOSFET has roughly 20–50x higher Rds(on) than a 100V device of the same die size. This rapid scaling with voltage is why IGBTs replace MOSFETs above 300–600V: at 1200V, Rds(on) of a MOSFET becomes prohibitively high, while an IGBT's conductivity modulation keeps the on-state voltage at 2–3V regardless of blocking voltage.

Follow-up: What is superjunction technology and how does it improve Rds(on) versus voltage rating?

Q3. What is the gate charge (Qg) of a Power MOSFET and why does it matter for switching?

Gate charge is the total charge that must be delivered to the gate to fully enhance the MOSFET from off to on, and it determines the gate driver current and switching time — a higher Qg requires more gate current for the same turn-on time. An IRF540N (100V, 33A MOSFET) has Qg = 71 nC; driven by a 1A gate driver, it charges in 71 ns, limiting the switching frequency where gate drive losses become significant. In a 100 kHz inverter, gate drive power dissipation is P_gate = Qg × Vgs × f = 71nC × 10V × 100kHz = 71 mW per device — multiplied by all switches in the bridge, this is a non-trivial loss budget.

Follow-up: What is the Miller plateau in the gate charge curve and what causes it?

Q4. What is the Miller effect in Power MOSFETs and how does it affect switching speed?

The Miller effect is the amplification of the drain-gate capacitance Cgd during switching transitions — as the drain voltage swings, the Cgd Miller capacitance reflects an effective large input capacitance that must be charged/discharged by the gate driver, slowing down the switching transition. During the turn-on dv/dt period of an IRFP260 in a 400V bus inverter, Cgd (5–15 nF at low Vds) causes the gate voltage to pause at the Miller plateau (~4V for N-channel) while the driver sources current entirely into Cgd to pull down the drain. A fast-switching driver with 2A source current reduces the Miller plateau duration and limits switching losses, while a weak 100 mA driver causes a long plateau and excessive Eon.

Follow-up: How do you select the gate resistor value for a Power MOSFET — what are the trade-offs?

Q5. What is the body diode in a Power MOSFET and how does it behave in a half-bridge?

The body diode is an intrinsic P-N junction formed between the body and drain in the MOSFET structure, with slow reverse recovery (trr of 200–500 ns for standard MOSFETs) that limits hard-switching half-bridge performance. In a synchronous buck converter, the body diode of the low-side MOSFET conducts during the dead time between high-side turn-off and low-side turn-on; when the low-side turns on, the body diode's stored minority charge causes a reverse recovery spike of 10–30A on top of the inductor current, stressing the device. SiC MOSFETs and GaN HEMTs have negligible body diode stored charge (essentially no minority carriers), which is why they enable dead times of 10–20 ns versus 100–200 ns for Si MOSFETs.

Follow-up: What is dead time in a half-bridge and why must it be set correctly?

Q6. What is an IGBT's tail current at turn-off and how does it create switching loss?

Tail current is the slow decay of collector current after the gate voltage falls to zero, caused by minority carrier recombination in the N-drift region that cannot be turned off instantly unlike majority carriers in a MOSFET. An FGA25N120ANTD (1200V, 25A IGBT) has a tail current that decays from peak over 500–1000 ns after gate turn-off; during this time the collector-emitter voltage has already risen to bus voltage (600V in a 600V inverter), creating an overlap of high voltage and residual current. The turn-off energy Eoff = (1/2)×Vce×I_tail×tail_time is typically 1–3 mJ for a 1200V IGBT at 25A — at 20 kHz switching frequency, this alone dissipates 20–60W per device.

Follow-up: What is the difference between punch-through IGBT and non-punch-through IGBT in terms of tail current?

Q7. What is the Safe Operating Area (SOA) of a power device and how do you use it?

The SOA is the region on the Vds-Id (or Vce-Ic) plane within which the device can be operated without damage, bounded by maximum current, maximum voltage, maximum power dissipation, and secondary breakdown limits. When designing a 600V motor drive with an IPM600B040 IGBT module, the SOA datasheet curve must confirm that the transient operating point (e.g., 600V, 40A for 100 µs during short circuit) lies within the SOA boundary. Exceeding the SOA during abnormal conditions like motor stall or short circuit causes thermal runaway or second breakdown even if instantaneous peak current is below the DC current rating.

Follow-up: What is second breakdown in bipolar and IGBT devices?

Q8. What is the threshold voltage (Vth) of a Power MOSFET and why does it matter in gate drive design?

Vth is the minimum gate-source voltage at which the channel begins to conduct; for most power N-channel MOSFETs it is 2–4V and varies with temperature (decreasing about 5–10 mV/°C). A gate driver that pulls the gate to only 6V (barely above Vth) runs the MOSFET in the linear region with high Rds(on), while driving to 10–15V ensures full enhancement and minimum conduction loss. In a noisy inverter environment, Vgs ringing from PCB inductance can momentarily pull the gate of the OFF device above Vth and cause shoot-through — adding a 22 Ω gate resistor and a gate-to-source Zener (e.g., BZX84C15) prevents spurious turn-on.

Follow-up: How does temperature affect Vth and Rds(on) — what is the implication for paralleling MOSFETs?

Q9. What is dv/dt immunity in an IGBT and what causes dv/dt-induced turn-on?

dv/dt immunity is the device's resistance to spurious self-turn-on caused by rapid voltage transients coupling through the gate-collector capacitance Cgc during the complementary switch's turn-on event. When the high-side IGBT of a bridge turns on and the bus voltage appears across the low-side's collector at a fast dv/dt = 10 kV/µs, the displacement current I = Cgc × dv/dt charges the gate of the low-side through the gate resistor, potentially lifting Vge above Vth. Adding a low-impedance negative gate bias (−5V to −15V in the off state) or reducing gate resistance (decreasing the RC time constant) improves dv/dt immunity and prevents shoot-through in high-speed inverter bridges.

Follow-up: What is shoot-through and what happens to the DC bus when it occurs in a half-bridge?

Q10. What is an IGBT module and what is the difference between discrete IGBT and a power module?

An IGBT module packages multiple IGBT chips and antiparallel diodes in a common substrate with shared cooling base, offering lower parasitic inductance, better thermal performance, and pre-matched characteristics compared to discrete devices. An ABB 5SNA1200G450300 module contains six 4500V/1200A IGBT chips in a press-pack housing for traction inverter applications, with stray inductance below 10 nH versus 30–50 nH for equivalent discretes on a PCB. The lower stray inductance of modules reduces switching overvoltage spikes (V = L × di/dt), which is critical at 1200A turn-off rates in train traction converters.

Follow-up: What is a press-pack IGBT and what is its advantage in traction applications?

Q11. How do you calculate switching losses in a Power MOSFET at a given frequency?

Turn-on energy Eon and turn-off energy Eoff are given in the datasheet (e.g., for an IRFP260: Eon=0.5 mJ, Eoff=0.3 mJ at 200V, 20A); total switching loss is P_sw = (Eon + Eoff) × f_sw. For a 100 kHz half-bridge using two IRFP260 MOSFETs: P_sw per device = 0.8 mJ × 100 kHz = 80W — this is the dominant loss and limits the design to lower frequencies or requires a heatsink rated for 160W total. Conduction loss is P_cond = Irms² × Rds(on) = (14A)² × 40 mΩ = 7.8W per device, demonstrating that at 100 kHz switching loss dominates over conduction loss by 10:1.

Follow-up: How does switching frequency selection affect the size of the output inductor in a buck converter?

Q12. What is a SiC MOSFET and how does it compare to a Si IGBT for inverter applications?

A SiC MOSFET is a silicon carbide unipolar device with Rds(on) roughly 100–300 mΩ at 1200V ratings (versus 2–3V saturation voltage for Si IGBT) and negligible minority carrier storage, enabling switching frequencies of 100 kHz versus 20–30 kHz for Si IGBTs with similar loss budgets. A Wolfspeed C3M0060065D (650V, 60A SiC MOSFET) achieves Eoff < 50 µJ versus 500–1000 µJ for a comparable Si IGBT, allowing a solar inverter to use a smaller output filter at 100 kHz while achieving higher efficiency. SiC enables 98.5–99% inverter efficiency versus 97–98% for Si IGBT designs at the same power level — the efficiency gain justifies SiC's 3–5x higher device cost in high-duty-cycle applications.

Follow-up: What gate voltage is required to fully enhance a SiC MOSFET and why is it higher than Si?

Q13. What is gate drive bootstrap circuit and how does it supply the high-side gate driver?

A bootstrap circuit charges a capacitor (Cboot = 100–470 nF) to approximately Vcc (15V) through a diode when the low-side switch is on and the switching node is near ground; when the high-side switch must turn on, this charged capacitor floats up to the bus voltage and supplies the gate driver referenced to the source of the high-side MOSFET. An IR2110 high-low side driver uses a 100 nF bootstrap capacitor from VS to VB; at 50 kHz with 50% duty cycle, the 100 nF charges to 15V in the 10 µs low-side on-time and supplies the high-side driver gate charge of 100 nC (for a 1 mF gate capacitance at 100V) without drooping more than 1.5V. The limitation of bootstrap is that it cannot supply the high-side driver at 100% duty cycle because the capacitor never gets to recharge.

Follow-up: What is the minimum off-time required for a bootstrap capacitor to recharge?

Q14. What is derating in power device selection and why is it important for reliability?

Derating means selecting a device rated for a higher voltage, current, or power than the nominal operating condition, providing margin against transient overshoots, temperature derating of rated values, and end-of-life parameter drift. For a 400V bus inverter, power MOSFETs should be rated for at least 600V (1.5× derating) to survive inductive kickback spikes of 100–150V above bus that occur during fast turn-off with 50 nH stray inductance. JEDEC reliability guidelines recommend operating power devices at no more than 80% of their rated continuous current and 75% of voltage rating for 10-year field reliability — exceeding these limits dramatically reduces MTTF (mean time to failure).

Follow-up: What is the MOSFET avalanche energy rating and why does it matter for derating?

Q15. What is thermal resistance and how do you calculate junction temperature of a power device?

Thermal resistance Rth(j-a) (junction to ambient) is the temperature rise in °C per watt of power dissipated; junction temperature Tj = Ta + P_total × Rth(j-a) where Ta is ambient temperature and P_total is total device losses. For an IPM600B040 IGBT dissipating 40W on a heatsink with Rth(j-c) = 0.4°C/W, thermal grease Rth(c-s) = 0.1°C/W, and heatsink Rth(s-a) = 1.5°C/W at 45°C ambient: Tj = 45 + 40×(0.4+0.1+1.5) = 45 + 80 = 125°C — exactly at the rated maximum, indicating the heatsink must be improved. Exceeding maximum Tj of 150°C causes irreversible device degradation within hours in silicon IGBTs.

Follow-up: What is thermal impedance (transient thermal resistance) and when do you use it instead of steady-state Rth?