VLSI Basics Interview Questions

Q1. What is CMOS and why has it dominated VLSI circuit design?

CMOS (Complementary Metal-Oxide-Semiconductor) uses complementary pairs of NMOS and PMOS transistors where one is always off during steady state, resulting in near-zero static power consumption — only dynamic power is dissipated during switching. A CMOS inverter draws current only during the brief transient when both transistors are partially on during a logic transition at 2.4 GHz (Apple A15), not during the stable 0 or 1 state. This near-zero static power scales with the number of gates: a 15 billion transistor chip using bipolar logic would dissipate kilowatts at rest, making cooling impossible, while CMOS dissipates only dynamic power proportional to activity.

Follow-up: What is the noise margin of a CMOS inverter and how does it relate to transistor sizing?

Q2. What is the VLSI design flow from specification to tape-out?

The standard digital VLSI flow is: RTL design (Verilog/VHDL) → functional simulation → synthesis (RTL to gate netlist using standard cell library) → DFT insertion (scan chains) → place and route (floor planning, placement, clock tree synthesis, routing) → timing closure (static timing analysis) → DRC/LVS verification → tape-out (GDSII to foundry). At Qualcomm, a Snapdragon baseband modem chip follows this flow using TSMC 5nm standard cells, with synthesis using Synopsys Design Compiler and place-and-route using Cadence Innovus. Each step has a sign-off criterion — timing must close with positive slack on all paths, and DRC must have zero violations before the GDSII is sent to the fab.

Follow-up: What is the difference between synthesis and place-and-route in the VLSI flow?

Q3. What is a standard cell library and how is it used in digital VLSI design?

A standard cell library is a characterized set of pre-designed logic gates (AND, OR, flip-flop, MUX, buffer) with fixed height and variable width, verified for a specific technology node, provided by the foundry or a third-party IP vendor with timing (Liberty .lib), layout (GDSII), and simulation (SPICE) models. In a 28nm TSMC design, the standard cell library from TSMC includes AND2, OR2, DFF cells where each cell's timing arcs (input-to-output delay at various slew and load) are characterized at SS/TT/FF corners at -40/25/125°C. The synthesis tool maps RTL statements to these cells, and the place-and-route tool instantiates their physical GDSII layouts to create the final chip layout.

Follow-up: What is a Liberty (.lib) file and what information does it contain?

Q4. What is setup time and hold time in a digital flip-flop and what happens when they are violated?

Setup time is the minimum time data must be stable before the clock edge, and hold time is the minimum time data must remain stable after the clock edge — these are the timing constraints that ensure the flip-flop captures data reliably. In a 28nm Samsung flip-flop, setup time is typically 50 ps and hold time 0 ps (or slightly negative), determined by the transistor delay of the master latch; violating setup time causes metastability where the output takes nanoseconds to resolve, corrupting the captured data. Static Timing Analysis (STA) in Cadence Tempus computes timing slack = (data arrival time) - (clock edge + setup time) for every flip-flop; negative slack indicates a setup violation that must be fixed by buffering, upsizing, or retiming.

Follow-up: What is metastability and how do synchronizers reduce its probability?

Q5. What is static timing analysis (STA) and why is simulation not sufficient for timing verification?

STA analyzes every combinational path in the design without simulation vectors, computing the worst-case delay through each path using cell delay models and checking against setup and hold constraints for every flip-flop. A chip with 10 million paths could never be exhaustively simulated to verify timing — even at 1 billion random vectors per second, full coverage would take years; STA checks all paths mathematically in hours. Synopsys PrimeTime is the industry-standard STA tool — at Samsung Austin, every chip undergoes multi-corner multi-mode STA analysis at all 9 PVT corners (slow-slow/-40°C, fast-fast/125°C, etc.) before tape-out sign-off.

Follow-up: What is multi-corner multi-mode (MCMM) analysis in STA?

Q6. What are the sources of power dissipation in a CMOS chip?

CMOS power has three components: dynamic switching power P_dyn = α×C×V²×f (switching capacitance charging/discharging), short-circuit power during transitions when both PMOS and NMOS are momentarily on, and leakage power P_leak = Ileak×V from subthreshold, gate oxide, and junction leakage. In a 5nm Apple A15, dynamic power dominates during computation (α×C×V²×f with V≈0.8V, f=3.2 GHz), but leakage is significant due to the very thin gate oxide and high transistor count — leakage in standby mode is 100–500 mW across the 15 billion transistors. Power optimization techniques include clock gating (reducing α), multi-Vt cells (reducing Ileak), and voltage scaling (reducing V quadratically).

Follow-up: What is clock gating and how does it reduce dynamic power?

Q7. What is the CMOS fabrication process — what are the key steps?

The key CMOS fabrication steps are: STI (Shallow Trench Isolation) to isolate transistors, well formation (N-well for PMOS), gate oxide growth (1–2 nm SiO2 or HfO2 high-k at 7nm), polysilicon or metal gate deposition and patterning, source/drain ion implantation, spacer formation, silicidation, contact/via formation, and multilayer metal interconnect (10–15 metal layers in 5nm TSMC N5). A 5nm gate length transistor at TSMC is defined by EUV (Extreme Ultraviolet) lithography at 13.5 nm wavelength, enabling sub-7nm patterning that was impossible with conventional 193nm DUV. Each photolithography step uses a mask — a 5nm chip may require 80–100 mask layers.

Follow-up: What is EUV lithography and why is it needed below 7nm technology node?

Q8. What is design rule check (DRC) and layout versus schematic (LVS)?

DRC verifies that the physical layout meets the foundry's minimum geometry rules (minimum width, spacing, overlap, enclosure for each layer) that ensure reliable manufacturability; LVS checks that the extracted netlist from the layout matches the schematic netlist, confirming no transistors are missing or incorrectly connected. A DRC violation like a metal1 space violation (two wires too close) at TSMC 7nm means the feature cannot be reliably patterned — the yield would drop significantly. LVS failures are often caused by floating nets, missing connections, or incorrect transistor sizing in the drawn layout, and must be resolved before tape-out or the manufactured chip will not function.

Follow-up: What is parasitic extraction (RC extraction) and why is it done after placement and routing?

Q9. What is clock tree synthesis (CTS) and why is clock skew a problem?

Clock tree synthesis builds a balanced tree of buffers to distribute the clock signal from the source to all flip-flops with minimal arrival time variation (skew), using symmetric H-tree or spine topologies with matched wire lengths and buffer sizes. In a 28nm design with 1 million flip-flops operating at 1 GHz, unconstrained clock distribution would cause 500–2000 ps of skew, adding directly to the setup time requirement and potentially causing timing failures; CTS targets skew < 50 ps using Cadence CCOpt or Synopsys ICCompiler. Clock tree power is a significant contributor — the clock network may consume 20–40% of total dynamic power, which is why clock gating cells are inserted to disable clock branches in idle functional blocks.

Follow-up: What is useful skew and how is it used to fix timing violations in a post-CTS design?

Q10. What is a latch-up in CMOS and how is it prevented?

Latch-up is a parasitic thyristor (PNPN) formed by the substrate and well structures that can trigger into a low-impedance conducting state, drawing destructive current and locking the circuit in the wrong logic state until power is cycled. In a CMOS inverter, the P-well/N-substrate/N-well/P-substrate forms a parasitic SCR that triggers if the substrate or well voltage is disturbed beyond the supply rails — typically caused by I/O voltage overshoots or ESD pulses. Prevention includes guard rings (N+ ring around PMOS in N-well and P+ ring around NMOS in P-substrate to collect minority carriers before they reach the parasitic base), and meeting minimum separation rules between NMOS and PMOS transistors as specified in the design rules.

Follow-up: What is ESD (Electrostatic Discharge) protection and what devices are used for it in VLSI I/O pads?

Q11. What is the difference between NMOS and PMOS transistors in CMOS and why are PMOS transistors wider?

NMOS transistors conduct with electrons (higher mobility: µn ≈ 450 cm²/Vs in bulk Si) while PMOS uses holes (lower mobility: µp ≈ 150 cm²/Vs), making NMOS approximately 2–3× faster per unit width. To achieve equal drive current (and thus equal rise and fall times in a CMOS gate), PMOS transistors are sized 2–3× wider than NMOS — a minimum NMOS of width W = 100 nm requires a PMOS of W = 200–300 nm for matched current. In a CMOS inverter, unequal sizing causes asymmetric rise and fall delays, which shifts the switching threshold away from VDD/2 and reduces noise margin — standard cell libraries use precisely characterized W_p/W_n ratios to achieve target slew symmetry.

Follow-up: What is the effect of sizing the PMOS transistor much wider than necessary in a CMOS gate?

Q12. What is voltage scaling and how does it reduce power — what are its limits?

Reducing VDD reduces dynamic power quadratically (P ∝ V²) and leakage power linearly, but slows logic delay as roughly D ∝ VDD / (VDD - Vth)² — a 10% VDD reduction gives about 19% power saving but 12% speed reduction. Apple A15 uses adaptive voltage scaling (AVS) to reduce VDD from 0.9V at maximum frequency to 0.6V at low workloads, saving 56% of dynamic power at reduced frequency. The fundamental limit of VDD scaling is the threshold voltage Vth (typically 0.3–0.4V in 5nm), below which subthreshold slope limits transistor switching speed — near-threshold computing at 0.4V is used in IoT chips like the ARM Cortex-M0+ in STM32L0 achieving < 100 µW active power at 1 MHz.

Follow-up: What is dynamic voltage and frequency scaling (DVFS) and how is it implemented in mobile SoCs?

Q13. What is the difference between synchronous and asynchronous reset in flip-flop design and which is preferred in VLSI?

A synchronous reset is applied only on the active clock edge (reset takes effect on the next clock cycle), while an asynchronous reset immediately forces the output regardless of the clock — in VLSI, synchronous reset is strongly preferred for timing analyzability and glitch immunity. With synchronous reset in Verilog: always @(posedge clk) if (rst) Q <= 0; — the reset path is just another data path that STA analyzes normally, and glitches on rst that don't coincide with the clock edge are ignored. Asynchronous reset complicates timing (requires false path exceptions), creates metastability risk during reset deassertion, and can cause unpredictable state if the reset pulse arrives at different times at different flip-flops during clock-domain crossing.

Follow-up: What is reset synchronization and why is it needed for asynchronous reset in a synchronous design?

Q14. What is a flip-flop versus a latch in digital design — which is used in standard VLSI designs?

A latch is level-sensitive and transparent when the enable (clock) is high, passing data continuously; a flip-flop is edge-triggered and captures data only at the clock edge, holding the value until the next edge. Standard synchronous VLSI designs exclusively use flip-flops (specifically positive-edge-triggered D flip-flops) because level-sensitive latches cause race conditions in STA and make timing closure unpredictable — two back-to-back latches on the same clock can allow data to ripple through multiple stages in one clock period. Latches are used intentionally in time-borrowing architectures or high-speed SRAM bit cells (6T SRAM uses cross-coupled inverters forming a latch) but never as general-purpose registers in standard cell synthesis flow.

Follow-up: What is time borrowing and in what circuits is latch-based design an advantage?

Q15. What is the threshold voltage Vth of a MOSFET in VLSI and why is controlling it critical?

Vth is the gate-source voltage at which the transistor begins to conduct a threshold amount of drain current (typically defined as 1 µA × W/L); in 5nm TSMC, nominal NMOS Vth ≈ 0.4V but varies ±50 mV die-to-die due to random dopant fluctuation (RDF) and line edge roughness. Vth variation directly affects both speed (subthreshold leakage exponentially depends on Vth: Ileak ∝ e^(-Vth/nVT)) and power — a 50 mV lower Vth than nominal increases leakage by 5–10× at room temperature. VLSI design uses multi-Vt cell libraries: HVT (high Vth) cells with lower leakage but slower speed for non-critical paths, SVT (standard) and LVT (low Vth, fast but leaky) cells on critical timing paths — mixing cell Vt types is the primary leakage optimization technique.

Follow-up: What is random dopant fluctuation (RDF) and why does it increase Vth variability at smaller nodes?