How it works
Quantum confinement occurs when a device dimension approaches the de Broglie wavelength of an electron (~10 nm in silicon). In a quantum well, the energy levels become discrete: En = (ℏ²π²n²)/(2m*L²), where L is the confinement dimension. Carbon nanotubes (CNTs) are rolled graphene sheets; an armchair (n,n) CNT is metallic and can carry current density exceeding 10⁹ A/cm² — far beyond copper's 10⁵ A/cm² limit. FinFETs (Intel 22 nm and beyond) use a thin silicon fin as the channel with the gate wrapping three sides, dramatically suppressing short-channel effects. Tunnel FETs exploit band-to-band tunnelling instead of thermionic emission, enabling sub-60 mV/decade subthreshold swing — below the classical room-temperature limit of 60 mV/decade for conventional MOSFETs.
Key points to remember
The classical MOSFET subthreshold slope limit is 60 mV/decade at 300 K — any conventional FET turns on faster than this cannot be made. Tunnel FETs and negative-capacitance FETs (using ferroelectric gate insulators) aim to break this limit for ultra-low-power IoT applications. At sub-5 nm gate lengths, source-to-drain tunnelling creates an off-state leakage floor that cannot be reduced by gate voltage alone. Single-electron transistors (SETs) operate by controlling individual electron charging of a Coulomb island; the charging energy e²/2C must exceed kT, requiring C in the attofarad range achievable only at cryogenic temperatures or with very small junctions. Graphene has zero bandgap natively — a transport gap is induced by cutting it into nanoribbons below ~10 nm width.
Exam tip
The examiner always asks you to explain why FinFETs replaced planar MOSFETs below 22 nm — state that the short-channel effects (DIBL, VT roll-off, subthreshold leakage) in a planar device cannot be controlled by a single-side gate at short lengths, and a three-sided fin gate provides better electrostatic control.