Short notes

SCR and Thyristor Short Notes

A 5 A, 200 V SCR — say the BT151 — controlling the average power delivered to a 100 W lamp from a 230 V AC supply will only conduct during the portion of each half-cycle after the gate pulse arrives at firing angle α. Change α from 30° to 90° and the lamp dims noticeably; this phase control is the foundation of every dimmer switch and motor speed controller using thyristors. Once the SCR latches ON, removing the gate pulse does nothing — current keeps flowing through the anode-cathode path until it drops below the holding current I_H.

EEE, ECE

How it works

The SCR is a four-layer PNPN device with three terminals: anode, cathode, and gate. It can be modelled as two transistors — a PNP (Q1) and an NPN (Q2) — connected in a regenerative feedback loop where Q1's collector drives Q2's base and vice versa. A positive gate pulse triggers Q2 into conduction, which drives Q1 on, which reinforces Q2 — the device snaps into a low-impedance conducting state in microseconds. Turn-off requires reducing anode current below holding current I_H (typically 5–30 mA) — in AC circuits, the natural current zero at the end of each half-cycle provides this commutation automatically.

Key points to remember

The SCR has four operating modes: forward blocking (V_AK > 0, gate off), forward conducting (triggered or breakover), reverse blocking, and reverse breakdown. Latching current I_L (typically 2–4× I_H) is the minimum anode current required to sustain conduction after the gate pulse is removed. Forward breakover voltage V_BO is the anode voltage at which the SCR self-triggers without a gate signal — normal operation keeps V_AK well below this. For forced commutation in DC circuits, a charged capacitor is switched across the SCR to temporarily reverse the anode current. Gate trigger current I_GT is typically 10–50 mA for standard SCRs.

Exam tip

Every Anna University power electronics and semiconductor devices paper asks you to draw the two-transistor model of an SCR and explain the regenerative latching mechanism — practice labelling Q1 (PNP), Q2 (NPN), and the feedback paths clearly.

More Semiconductor Devices notes