How it works
The Cortex-M3 has a 3-stage pipeline (fetch, decode, execute) with Harvard architecture (separate instruction and data buses). The 32-bit Thumb-2 instruction set mixes 16-bit and 32-bit instructions in the same code stream, achieving code density close to ARM Thumb while retaining full 32-bit performance — no mode switching needed. Registers: R0–R12 are general-purpose; R13 is SP (stack pointer, two banked: MSP and PSP); R14 is LR (link register, saves return address); R15 is PC (program counter). The NVIC (Nested Vectored Interrupt Controller) handles up to 240 external interrupts with programmable priorities (0–255, lower number = higher priority) and latency as low as 12 cycles.
Key points to remember
Memory map is fixed and standard across all Cortex-M devices: 0x00000000–0x1FFFFFFF code region; 0x20000000–0x3FFFFFFF SRAM; 0x40000000–0x5FFFFFFF peripheral registers; 0xE0000000–0xFFFFFFFF system region (NVIC, SysTick, debug). SysTick is a 24-bit down-counter clocked from the core clock — interrupt every 1 ms requires reload value = 72000 − 1 for a 72 MHz core. Exception numbers 1–15 are system exceptions (Reset, NMI, HardFault, SVC, PendSV, SysTick); 16 and above are external interrupts. The MPU (memory protection unit) on Cortex-M3/M4 enforces memory access permissions for RTOS tasks.
Exam tip
Every Anna University embedded systems paper asks you to describe the Cortex-M exception handling sequence — explain that on exception entry the processor pushes R0–R3, R12, LR, PC, xPSR onto the stack automatically (8 words), then fetches the handler address from the vector table at 0x00000004 + (exception number × 4).