How it works
The timer counts from 0 up to the ARR value, then resets — this period determines PWM frequency: f = f_clk / ((PSC+1)(ARR+1)). The CCR register sets the compare threshold; when the counter matches CCR, the output pin toggles. With ARR = 999 and CCR = 499, duty cycle is 50%. TIM1 is an advanced timer with complementary outputs used for motor H-bridge control with dead-time insertion, while TIM6 and TIM7 are basic timers with no output channels, used only to trigger DAC or generate update interrupts at precise intervals.
Key points to remember
PWM frequency and duty cycle are independently controlled via ARR and CCR respectively. A prescaler value of 0 means divide-by-1, so PSC = 83 divides an 84 MHz clock to exactly 1 MHz. Duty cycle (%) = (CCR / (ARR+1)) × 100. TIM1 supports up to 6 channels with complementary pairs and programmable dead-time, important for inverter circuits. Input capture mode uses the same timer hardware to measure the width of an incoming pulse — examiners often ask this in a separate sub-question about frequency measurement.
Exam tip
Every Anna University embedded systems paper has a numerical asking you to calculate ARR and PSC values for a required PWM frequency, so practice the formula f = f_clk / ((PSC+1)(ARR+1)) until you can rearrange it blindfolded.