How it works
When EXTI0 fires, the NVIC checks its priority register — say, priority level 2 — against whatever ISR is currently running. If the active ISR has a numerically higher value (lower urgency), the NVIC preempts it, saves eight registers onto the stack automatically, and vectors to the ISR address stored in the vector table at offset 0x58. Inside the ISR, you clear the pending bit in EXTI_PR before returning; forgetting this causes the interrupt to re-trigger immediately. The NVIC on Cortex-M supports up to 240 external interrupts, configurable through NVIC_IPR registers with 4-bit priority fields.
Key points to remember
The NVIC supports up to 240 maskable interrupts on Cortex-M4, though STM32 devices typically expose 60–90. Priority values are 4 bits wide, so levels 0–15 are valid — level 0 is highest priority. Preemption happens only when the incoming interrupt's preempt priority is strictly lower in number than the active one; sub-priority breaks ties. Tail-chaining is a key efficiency feature: back-to-back interrupts skip the full push-pop cycle, saving 12 cycles. The SysTick interrupt at priority 15 is commonly used for RTOS tick generation.
Exam tip
The examiner always asks you to distinguish between preempt priority and sub-priority in NVIC, and at least one Anna University paper has asked you to calculate which ISR runs first when two interrupts arrive simultaneously with given priority values.