How it works
A transaction begins when the master pulls SDA low while SCL is high — that is the START condition. The master then clocks out a 7-bit address plus a read/write bit; the addressed slave pulls SDA low for one clock cycle to ACK. In write mode, data bytes follow with ACK after each one; in read mode, the master releases SDA and the slave drives it. Clock stretching lets a slow slave hold SCL low to pause the master. Standard mode runs at 100 kHz; fast mode at 400 kHz; fast-mode plus reaches 1 MHz using lower pull-up resistor values around 1 kΩ.
Key points to remember
I2C supports up to 127 devices on a single bus using 7-bit addressing (10-bit addressing extends this to 1023). Pull-up resistor value directly affects rise time — 4.7 kΩ is standard for 100 kHz, while 400 kHz mode typically needs 2.2 kΩ or lower. A missing ACK causes the master to abort the transaction and set the AF (Acknowledge Failure) flag in the I2C status register. Repeated START allows a master to change direction from write to read without releasing the bus, essential for register-read operations on devices like the BMP280 sensor.
Exam tip
The examiner always asks you to draw the complete I2C waveform for writing one byte to a slave, including START, address, R/W bit, ACK, data byte, ACK, and STOP — practice drawing this from memory.