How it works
The master generates SCK; data shifts out on MOSI and in on MISO simultaneously — SPI is full-duplex by default. CPOL and CPHA together define the clock mode: CPOL=0, CPHA=0 (Mode 0) means clock idles low and data is sampled on the rising edge, which the W25Q32 flash chip uses. The master pulls NSS low to select a slave, transfers N clock pulses, then raises NSS. SPI_DR is written to start transmission; the BSY flag stays high until the shift register is completely empty — polling BSY before de-asserting NSS prevents incomplete transfers.
Key points to remember
SPI has four clock modes defined by CPOL and CPHA combinations — Mode 0 (0,0) is the most common, used by devices like the MPU-6050 in SPI mode and most SPI flash chips. Unlike I2C, SPI has no addressing scheme; device selection is purely hardware using NSS lines, so ten SPI devices need ten separate chip-select pins. Theoretical max speed on STM32F4 SPI1 is 42 MHz (APB2 / 2). SPI does not support multi-master configurations without external arbitration. Data can be 8-bit or 16-bit per frame, selectable via DFF bit in SPI_CR1.
Exam tip
Every board exam and internal test has a question asking you to compare SPI and I2C — know that SPI is faster and full-duplex but needs more pins, while I2C supports multiple masters on two wires but tops out around 3.4 MHz in high-speed mode.