How it works
A DMA transfer needs three addresses: the peripheral data register address (ADC1->DR), the memory destination address, and the transfer count. The DMA controller arbitrates between channels using fixed or programmable priority — on STM32, DMA1 has 7 channels with round-robin arbitration at equal priority. In normal mode, the DMA stops after the configured number of transfers; in circular mode, it wraps back to the start address automatically. Memory-to-memory mode moves data between two RAM regions without any peripheral involvement, useful for fast buffer copies at speeds limited only by the AHB bus bandwidth.
Key points to remember
DMA operates independently of the CPU on the AHB bus, so it competes with the CPU for RAM access — this is called bus contention and can stall the CPU for one cycle per DMA access. Transfer width can be 8-bit, 16-bit, or 32-bit; mismatched source and destination widths are automatically padded or truncated by the hardware. Double-buffer mode (available on DMA2 on STM32F4) switches between two memory buffers automatically, giving the CPU time to process one buffer while DMA fills the other. DMA error flags — transfer error (TE) and FIFO error — must be cleared in software before restarting a transfer.
Exam tip
The examiner always asks you to explain why DMA is preferred over interrupt-driven data transfer for high-speed peripherals like ADC and UART at high baud rates — be ready with a specific example involving transfer rate and CPU utilisation numbers.