How it works
The Power MOSFET uses a vertical DMOS structure: current flows vertically from drain (bottom) through the N-drift region, through the P-body (controlled by the gate), and out the source (top). The N-drift region is lightly doped to support high V_DSS; thicker drift regions mean higher breakdown voltage but also higher R_DS(on). Gate oxide insulation means virtually zero gate current in steady state — only transient current charges and discharges C_iss = C_gs + C_gd. Turn-on requires charging the gate past threshold (~3–4 V for logic-level FETs, ~4–6 V for standard), then through the Miller plateau as C_gd discharges and V_DS collapses.
Key points to remember
R_DS(on) increases with temperature — approximately as T^2.3 — which can cause thermal runaway if not managed. The body diode (anti-parallel between drain and source) conducts reverse current with V_f ≈ 0.7–1.2 V; in synchronous rectifier designs, the MOSFET channel is turned on to bypass the body diode and reduce conduction loss. Switching losses P_sw ≈ ½·V_DS·I_D·(t_r+t_f)·f_sw dominate at high switching frequency while conduction loss P_cond = I_D²·R_DS(on) dominates at low frequency. Safe Operating Area (SOA) defines the V_DS vs I_D boundary within which the device does not fail due to thermal or electrical stress.
Exam tip
The examiner always asks you to explain why Power MOSFETs have positive temperature coefficient of R_DS(on) and how this property makes them safer to parallel compared to BJTs — know that as temperature rises, R_DS(on) increases, which reduces current and acts as self-balancing between paralleled devices.