Interview questions & answers
Q1. What is the basic architecture of the 8085 microprocessor?
The 8085 is an 8-bit microprocessor with a 16-bit address bus, 8-bit data bus, one accumulator, six general-purpose registers (B, C, D, E, H, L), a 16-bit stack pointer, 16-bit program counter, and an ALU with a flag register. Intel's original 8085 ran at up to 3 MHz on a 5V supply and was fabricated in NMOS technology. The multiplexed lower address bus and data bus on pins AD0–AD7 was a deliberate pin-count reduction that forced all designs to use an external latch like the 74LS373.
Follow-up: Why was the address bus and data bus multiplexed on the 8085?
Q2. What is the function of the ALE signal in the 8085?
ALE (Address Latch Enable) is a high pulse that the 8085 generates at the start of every machine cycle to indicate that the lower 8 bits of the address are currently valid on the AD0–AD7 pins, so an external latch can capture them before the bus becomes a data bus. The 74LS373 octal transparent latch is the standard demultiplexing chip, with its LE pin connected directly to ALE. Without latching on ALE, the lower address bits are lost when the bus switches to data mode and memory decoding fails.
Follow-up: What would happen if the ALE pulse width were too narrow for the latch setup time?
Q3. What are the registers in the 8085 and what are their sizes?
The 8085 has an 8-bit accumulator A, six 8-bit general-purpose registers B, C, D, E, H, L that can pair as 16-bit BC, DE, and HL pairs, a 16-bit stack pointer SP, a 16-bit program counter PC, and an 8-bit flag register F. The HL pair is the most versatile because it can be used as a memory pointer directly in instructions like MOV M, A without a separate addressing mode instruction. The flag register holds only 5 of its 8 bits: Sign, Zero, Auxiliary Carry, Parity, and Carry.
Follow-up: Which register pair is used as a memory data pointer, and what instruction directly uses it?
Q4. What is the function of the program counter in the 8085?
The program counter holds the 16-bit address of the next instruction byte to be fetched from memory, and it increments automatically after each byte is fetched. At reset, the PC is cleared to 0000H, so the 8085 always fetches its first instruction from memory address 0000H. Because the PC is 16 bits wide, the 8085 can directly address 64 KB of memory without any bank switching.
Follow-up: What happens to the program counter when a CALL instruction is executed?
Q5. What is the stack and how does the stack pointer work in the 8085?
The stack is a LIFO data structure in RAM used to save register contents and return addresses, and the stack pointer is a 16-bit register that always points to the top of the stack which is the last occupied location. In a typical 8085 system, the stack is placed at the top of RAM — for an 8 KB RAM ending at 3FFFH, the SP is initialized to 4000H so the first PUSH decrements it to 3FFEH before writing. The stack grows downward (toward lower addresses) with each PUSH and shrinks upward with each POP.
Follow-up: What happens if the stack overflows into the program code area?
Q6. What are the five flags in the 8085 flag register?
The five flags are Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY), each set or cleared based on the result of ALU operations. The Auxiliary Carry flag is set when there is a carry from bit 3 to bit 4, and it is used exclusively by the DAA instruction for BCD arithmetic correction. Logical instructions like ANA and ORA clear the Carry and AC flags and set Parity and Sign based on the result, which is a common exam trap.
Follow-up: Which instructions do not affect the flag register at all?
Q7. What is the difference between the 8085's data bus and address bus?
The address bus is 16 bits wide and unidirectional — the 8085 only drives addresses onto it — while the data bus is 8 bits wide and bidirectional because it carries both read data from memory and write data to memory or I/O. The upper 8 address bits A8–A15 have dedicated pins, but A0–A7 are multiplexed with D0–D7 on the AD0–AD7 pins to reduce the package from a 48-pin to a 40-pin DIP. This multiplexing was the single most significant compromise in 8085 pin design.
Follow-up: How many memory locations can the 8085 address directly, and how is this calculated?
Q8. What is the role of the serial I/O pins SID and SOD on the 8085?
SID (Serial Input Data) and SOD (Serial Output Data) are single-bit pins that implement a simple software-controlled serial interface using the RIM and SIM instructions respectively. The SIM instruction can output one bit on SOD by writing a byte with bit D7 set and the desired output level in D6, making it possible to bit-bang a UART in software at speeds determined entirely by the instruction execution loop. This feature allowed the 8085 to communicate serially with TTY terminals and slow peripherals without any external UART chip.
Follow-up: What is the maximum reliable baud rate achievable using the SID/SOD software serial interface?
Q9. What is the difference between I/O-mapped I/O and memory-mapped I/O in the 8085?
In I/O-mapped I/O (isolated I/O), the 8085 uses IN and OUT instructions that generate a separate IO/M# low signal and place an 8-bit port address on both A0–A7 and A8–A15, accessing up to 256 ports. In memory-mapped I/O, I/O devices are assigned memory addresses and accessed with MOV instructions, giving them access to all addressing modes but consuming memory address space. Memory-mapped I/O is simpler to decode but wastes address space; isolated I/O keeps the two spaces completely separate.
Follow-up: What is the maximum number of I/O ports addressable in 8085 isolated I/O mode?
Q10. What is the function of HOLD and HLDA pins in the 8085?
HOLD is an input from a DMA controller requesting control of the buses; when the 8085 finishes its current bus cycle it floats AD0–AD7, A8–A15, RD#, WR#, and IO/M# and asserts HLDA to confirm the bus release. The Intel 8237 DMA controller uses exactly this handshake to perform direct memory-to-memory or I/O-to-memory transfers without CPU intervention, typically for high-speed peripheral data like disk or video. While HOLD is asserted, the CPU is completely halted but internal registers and the program counter retain their values.
Follow-up: Can the 8085 execute instructions from its internal pipeline while another device holds the bus?
Q11. What is the function of the READY pin?
READY is an input that a slow memory or peripheral drives low to insert wait states, forcing the 8085 to extend the current machine cycle until READY returns high. A 2 MHz 8085 has a 500 ns machine cycle, and an EPROM with 450 ns access time would need one wait state inserted via READY to satisfy its timing requirement. Modern systems rarely need READY because fast SRAM and Flash devices respond well within a single machine cycle.
Follow-up: How many wait states can theoretically be inserted in a single machine cycle?
Q12. What is the reset mechanism of the 8085?
The 8085 has two reset inputs: RESET IN, which is the main reset that clears the PC to 0000H, clears the interrupt enable flip-flop, and resets all internal state; and RESET OUT, which is an output that goes high during reset so the CPU can reset external peripherals simultaneously. On power-up, an RC network connected to RESET IN holds the pin low long enough for the power supply to stabilize before the 8085 starts executing. RESET IN is active-low and Schmitt-triggered on later versions to handle slow power-up edges.
Follow-up: What is the minimum duration RESET IN must be held low to guarantee a complete reset?
Q13. How many machine cycles does a typical 8085 instruction take?
An 8085 machine cycle is the time to perform one bus operation, and most instructions take 1 to 5 machine cycles: a simple MOV r1, r2 takes 1 machine cycle (4 T-states), a memory fetch like MOV A, M takes 2 machine cycles (7 T-states total), and a CALL instruction takes 5 machine cycles (18 T-states). At 3 MHz, a T-state is 333 ns, so a CALL takes about 6 µs — important for calculating worst-case interrupt response time. The distinction between machine cycles and T-states is a common interview trap.
Follow-up: What is the difference between a T-state and a machine cycle?
Q14. What is the role of the accumulator in the 8085?
The accumulator is the primary 8-bit register for all ALU operations — addition, subtraction, AND, OR, XOR, complement, and rotate — and one of its operands is always the accumulator. When you execute ADD B, the ALU adds the accumulator and register B and stores the result back in the accumulator, destroying the previous value. All I/O instructions IN and OUT also transfer data through the accumulator, making it a bottleneck that forces the programmer to save and restore it frequently.
Follow-up: Can the 8085 perform arithmetic between two general-purpose registers without using the accumulator?
Q15. What is the significance of the 8085 being called an 8-bit processor?
The 8085 processes data in 8-bit chunks — its ALU, accumulator, and data bus are all 8 bits wide — though it uses a 16-bit address bus and can handle 16-bit data with paired register instructions like DAD (double add) and INX. A 16-bit addition like adding two 16-bit numbers requires two 8-bit additions with the Carry flag propagating from the low byte to the high byte using ADC. This distinction between data word size and address width is fundamental to understanding why the 8085 can address 64 KB despite being an 8-bit processor.
Follow-up: How does the 8085 perform 16-bit arithmetic using its 8-bit ALU?
Common misconceptions
Misconception: The 8085 has a 16-bit data bus because it has 16-bit register pairs.
Correct: The 8085 data bus is strictly 8 bits wide; the 16-bit register pairs are internal to the CPU and do not correspond to bus width.
Misconception: ALE is used to enable memory chip select directly.
Correct: ALE only indicates that valid lower address bits are on AD0–AD7; it drives a transparent latch like the 74LS373 to demultiplex the bus, not memory chips directly.
Misconception: The stack pointer points to the next empty stack location.
Correct: In the 8085 the stack pointer always points to the last filled (top) location; a PUSH first decrements SP then writes, so SP always contains a valid data address after any push.
Misconception: RESET clears all registers including general-purpose registers.
Correct: RESET IN clears only the PC, the interrupt enable flip-flop, and the HLDA state; registers B, C, D, E, H, L, and the accumulator retain their previous values after reset.