8085 Interrupts Interview Questions

Q1. What are the interrupts available in the 8085 and what are their priorities?

The 8085 has five hardware interrupts in descending priority: TRAP (highest), RST 7.5, RST 6.5, RST 5.5, and INTR (lowest). TRAP is non-maskable and always active; RST 7.5, 6.5, and 5.5 are maskable via the SIM instruction; INTR is maskable and requires external encoding logic like an 8259A to generate the restart vector. Priority is fixed in hardware — TRAP is always serviced before RST 7.5 even if both arrive simultaneously.

Follow-up: If RST 6.5 and RST 5.5 arrive at the same time, which one is serviced first?

Q2. What is the TRAP interrupt and why is it special?

TRAP is the only non-maskable interrupt in the 8085, level-and-edge triggered, and vectors unconditionally to address 0024H regardless of the interrupt enable flip-flop or the SIM mask register. It is edge-and-level triggered meaning it requires both a low-to-high transition and the signal remaining high to be recognized, preventing false triggering from glitches or continuous logic levels. In practice, TRAP is connected to a power-fail detector so the CPU can save critical state to battery-backed RAM before the supply drops below the operating threshold.

Follow-up: Why is TRAP both edge-triggered and level-sensitive rather than purely edge-triggered like RST 7.5?

Q3. What are the vectored addresses for each 8085 interrupt?

TRAP vectors to 0024H, RST 7.5 to 003CH, RST 6.5 to 0034H, RST 5.5 to 002CH, and INTR to the address determined by the restart instruction placed on the data bus by external hardware. These 8-byte gaps between vectors are just large enough for a 3-byte JMP instruction and a few NOPs, or just a JMP to the actual ISR elsewhere in memory. Forgetting that TRAP is at 0024H and not 0020H is a common exam error because the gap is irregular.

Follow-up: How many bytes are available between each vectored interrupt address?

Q4. What is the difference between RST 7.5 and RST 6.5 in terms of triggering?

RST 7.5 is edge-triggered — it is recognized on a rising edge and an internal flip-flop holds the request until serviced even if the signal returns low — while RST 6.5 and RST 5.5 are level-triggered and must remain high until the CPU acknowledges them. For RST 7.5, the request flip-flop can be cleared by the SIM instruction with the RST 7.5 reset bit set, even without servicing the interrupt. This edge-triggered latch means RST 7.5 can capture a short pulse that would be missed by a level-triggered input.

Follow-up: What happens if RST 7.5 fires and is never serviced while the signal returns low?

Q5. What is the SIM instruction and how is it used for interrupt masking?

SIM (Set Interrupt Mask) is an 8085 instruction that interprets the accumulator content to set mask bits for RST 7.5, RST 6.5, and RST 5.5 and to output one serial bit on SOD. To disable RST 6.5 and RST 5.5 while leaving RST 7.5 enabled, load the accumulator with 06H (00000110B with MSE bit D3 set as 1 making it 0EH) and execute SIM. A common bug is loading SIM without setting bit D3 (Mask Set Enable), which causes the mask bits to be ignored even though SIM executes without error.

Follow-up: What bit in the SIM byte must be set for the mask bits to take effect?

Q6. What is the RIM instruction and what information does it provide?

RIM (Read Interrupt Mask) loads the accumulator with the current state of the interrupt masks for RST 7.5, 6.5, 5.5 in bits D0–D2, the interrupt enable flag in D3, the pending interrupt flags in D4–D6, and the current logic level of SID in D7. By executing RIM and checking bit D6, you can determine whether an RST 7.5 interrupt is pending without waiting for it to be serviced. RIM is the only way to read back the interrupt mask state that was previously set by SIM.

Follow-up: If you execute RIM and bit D4 is set, what does that indicate?

Q7. What happens to the interrupt enable flip-flop when the 8085 services an interrupt?

The 8085 automatically clears the interrupt enable flip-flop (disables maskable interrupts) when it acknowledges an interrupt, preventing the current ISR from being interrupted by another maskable interrupt at the same or lower priority. The ISR must explicitly execute EI before RET if it wants to allow other interrupts to nest, or rely on the RET to restore operation without re-enabling. Forgetting EI in a time-critical system means all subsequent maskable interrupts are permanently lost after the first one.

Follow-up: Does acknowledging TRAP also disable the interrupt enable flip-flop?

Q8. How does the INTR interrupt work and what external hardware does it require?

INTR is a level-triggered maskable interrupt that, when acknowledged by the 8085, causes the CPU to float the data bus for one cycle and then latch whatever the external hardware places on it as a restart instruction, typically RST 0 through RST 7. An Intel 8259A priority interrupt controller interfaces up to 8 external devices, encodes their priorities, and places the correct RST opcode on the bus during the INTA cycle. Without the 8259A or equivalent circuitry, using INTR requires discrete logic to generate the restart instruction on the bus.

Follow-up: What opcode must appear on the data bus during the INTA acknowledge cycle for INTR to vector to 0018H?

Q9. What is an interrupt service routine and what must it do before returning?

An ISR is the code executed in response to an interrupt; it must save all registers it modifies using PUSH, service the interrupt source, clear the interrupt request at the peripheral if level-triggered, execute EI if maskable interrupts should be re-enabled, and return with RET. In an 8085 keyboard scanner ISR, the routine typically executes PUSH PSW, PUSH B, PUSH H to save state, reads the key code, stores it in a RAM buffer, clears the keyboard interrupt line, executes EI, then pops registers in reverse order before RET. Mismatched PUSH and POP counts corrupt the stack and cause the RET to jump to a garbage address.

Follow-up: Why must registers be popped in the exact reverse order they were pushed?

Q10. What is interrupt latency in the 8085 and what factors affect it?

Interrupt latency is the time from when an interrupt is asserted to when the first instruction of the ISR executes, and it is determined by the current instruction's remaining T-states plus the time to push the return address and vector to the ISR. The worst case is when a CALL or XTHL instruction (up to 18 T-states) is executing at 3 MHz, adding 6 µs to the minimum 12 T-state response overhead for a total of about 10 µs. Applications like motor control or data acquisition with strict real-time deadlines must account for worst-case latency, not average latency.

Follow-up: How do you reduce worst-case interrupt latency in an 8085 system?

Q11. How does the 8085 handle multiple simultaneous interrupts?

When multiple interrupts occur simultaneously, the 8085 services them in strict hardware priority order: TRAP first, then RST 7.5, RST 6.5, RST 5.5, then INTR. Only one interrupt is acknowledged per machine cycle; after the highest-priority ISR begins, it must execute EI to allow lower-priority interrupts to interrupt it, otherwise they queue until the ISR completes and the main program re-enables interrupts. This fixed priority cannot be changed in hardware but can be modified in software by selectively masking higher-priority sources within an ISR.

Follow-up: How would you implement a software-controlled priority scheme using the SIM instruction?

Q12. What is the purpose of the EI instruction at the start of an ISR?

EI re-enables maskable interrupts so that higher-priority interrupts can preempt the current ISR, implementing nested interrupt handling — but placing EI at the very start of an ISR is dangerous because it allows the same interrupt to immediately re-enter the ISR before the current invocation has saved registers. The correct practice is to execute all register saves and clear the interrupt source at the peripheral first, then execute EI if nesting is needed. Placing EI before PUSH PSW has caused subtle ISR re-entrancy bugs in real 8085 systems.

Follow-up: What is the minimum set of instructions that must execute before EI in a safely nested ISR?

Q13. How does TRAP differ from RST instructions used in software?

TRAP is a hardware interrupt pin that vectors to 0024H automatically; RST 0 through RST 7 are 1-byte software instructions that the programmer places in code to generate a restart to a fixed address from 0000H to 0038H in steps of 8H. RST 5 in software always vectors to 0028H with no latency overhead beyond the instruction's 12 T-states, while TRAP as hardware requires the 8085 to finish the current instruction and save the PC. Software RST instructions are used for breakpoints in monitor programs like the Intel MDS debugger.

Follow-up: What is the vector address of RST 3 when used as a software instruction?

Q14. What happens when the 8085 receives an interrupt while in the HLT state?

An unmasked interrupt pulls the 8085 out of the HALT state — the CPU resumes, acknowledges the interrupt, pushes the PC (pointing to the instruction after HLT) onto the stack, and vectors to the ISR. TRAP always wakes the CPU from HALT regardless of DI. In low-power keyboard-scan designs, the main program deliberately executes HLT after processing each keystroke and relies on the next keypress interrupt to resume, effectively creating an event-driven loop with near-zero idle power.

Follow-up: After the ISR executes RET, where does the 8085 return to — before or after the HLT instruction?