8086 Microprocessor Interview Questions

Q1. What are the key differences between the 8085 and 8086?

The 8086 is a 16-bit processor with a 20-bit address bus (1 MB addressing), a 6-byte instruction prefetch queue, segmented memory, and a minimum/maximum mode pin, while the 8085 is 8-bit with a 16-bit address bus and no pipelining. The 8086 executes instructions in parallel with fetching through its BIU and EU pipeline, making its effective throughput much higher than the 8085 for computation-heavy tasks. The 20-bit physical address is formed by shifting the segment register left by 4 and adding the 16-bit offset, a scheme that no simple 8-bit processor concept supports.

Follow-up: Why was the segmented memory model chosen instead of a full 20-bit flat address space?

Q2. What is the segmented memory model of the 8086?

The 8086 divides its 1 MB address space into logical segments — code, data, stack, and extra — each up to 64 KB, addressed by a 16-bit segment register and a 16-bit offset that are combined as physical address = (segment register × 16) + offset. The CS:IP pair always points to the next instruction, SS:SP always points to the top of the stack, DS is the default for most data operations, and ES is used by string instructions. Two different segment:offset values can point to the same physical address, a source of subtle aliasing bugs in segmented programs.

Follow-up: What is the maximum overlap between two different segment:offset addresses that map to the same physical address?

Q3. What are the segment registers of the 8086 and what are their roles?

The four 16-bit segment registers are CS (Code Segment — base of currently executing code), DS (Data Segment — default for most data reads and writes), SS (Stack Segment — base of the stack), and ES (Extra Segment — used by string operations MOVS, CMPS, STOS, and LODS for the destination address). On reset, CS is set to FFFFH and IP to 0000H, so the first instruction fetches from physical address FFFF0H which is typically a jump in ROM. Changing CS requires a far JMP or far CALL; direct MOV to CS is not allowed.

Follow-up: How do you change the code segment register to execute code in a different segment?

Q4. What is the difference between minimum mode and maximum mode in the 8086?

Minimum mode (MN/MX# pin tied high) is for single-processor systems where the 8086 generates all bus control signals directly on its own pins, while maximum mode (MN/MX# tied low) is for multiprocessor or coprocessor systems where an Intel 8288 Bus Controller chip decodes the status pins S0–S2 and generates the bus control signals. In minimum mode, the 8086 directly drives MEMR#, MEMW#, IOR#, IOW# and ALE; in maximum mode these pins become QS0, QS1, S0, S1, S2, LOCK#, and RQ/GT0#/GT1# for the bus arbiter. Most textbook lab kits use minimum mode with direct control signals.

Follow-up: What is the role of the 8288 Bus Controller chip in maximum mode?

Q5. What is the function of the BIU and EU in the 8086?

The Bus Interface Unit (BIU) fetches instructions from memory into a 6-byte prefetch queue and handles all bus transactions including memory reads, memory writes, and I/O, while the Execution Unit (EU) decodes and executes instructions from the queue without waiting for bus cycles. When the EU is executing a long instruction, the BIU fills the prefetch queue with the next instructions, effectively overlapping fetch and execute in a 2-stage pipeline. If the EU takes a branch, the prefetch queue is flushed and the BIU must refill it from the new address, causing a branch penalty of several clock cycles.

Follow-up: How many bytes can the 6-byte prefetch queue hold, and what determines when the BIU fetches a new instruction?

Q6. What is the physical address calculation in the 8086?

Physical address = (Segment Register × 16) + Offset, where multiplying by 16 is equivalent to shifting the 16-bit segment value left by 4 bits, generating a 20-bit base address, and the 16-bit offset is added. If DS = 1000H and a MOV instruction uses an offset of 0200H, the physical address is 10200H. This scheme allows a 16-bit processor with 16-bit registers to address 20 bits (1 MB) of memory, but it means every data access requires the segment register to be loaded with the correct value first.

Follow-up: What is the physical address when CS = F000H and IP = FFF0H?

Q7. What are the general-purpose registers of the 8086?

The 8086 has four 16-bit general-purpose registers AX, BX, CX, and DX, each split into 8-bit high and low halves (AH/AL, BH/BL, CH/CL, DH/DL), plus four 16-bit pointer and index registers: SP, BP, SI, and DI. AX is the primary accumulator for MUL, DIV, and I/O; CX is used as a loop counter by the LOOP instruction and string repeat prefix REP; BX is the only general-purpose register that can be used as a memory base pointer in addressing modes. The ability to access 8-bit halves of 16-bit registers was a significant advantage over the 8085 for byte-manipulation code.

Follow-up: Which 8086 register is used as the counter in the LOOP instruction?

Q8. What is the instruction queue in the 8086 and why is it important?

The instruction queue is a 6-byte FIFO inside the BIU that holds prefetched instruction bytes so the EU can start decoding the next instruction before the bus is free, implementing a simple pipeline. When the queue has 2 or more empty bytes, the BIU initiates a fetch; when the EU branches, the queue is flushed and refilled from the branch target. Without the prefetch queue, every instruction would stall waiting for a bus fetch, and the 8086's actual throughput would be similar to the 8085 despite its faster clock.

Follow-up: What is the queue flush condition and what performance impact does it have?

Q9. How does the 8086 handle 16-bit memory accesses at odd addresses?

The 8086 has a 16-bit data bus with a byte-high-enable signal BHE# that, combined with A0, selects which byte(s) of the data bus are active; accessing a word at an odd address requires two bus cycles instead of one because the word straddles two 16-bit aligned slots. A 16-bit word at address 1001H (odd) requires one cycle for the byte at 1001H using BHE# and another cycle for the byte at 1002H using A0, doubling the access time. In time-critical embedded systems, the linker is configured to align 16-bit data variables to even addresses.

Follow-up: How does the 80286 hardware handle misaligned word accesses compared to the 8086?

Q10. What is the difference between near, far, and intersegment jumps in the 8086?

A near JMP changes only the IP register and stays within the current code segment (CS unchanged), a far JMP changes both CS and IP to jump to a different segment, and intersegment is another name for far. Near JMPs are 2 or 3 bytes and execute in 15 T-states; far JMPs are 5 bytes and require a segment register reload costing about 24 T-states. The distinction is critical in modular assembly programs where calling subroutines in different code segments requires far CALL and far RET, with the stack containing both CS and IP for the return.

Follow-up: How many bytes does a far CALL push onto the stack compared to a near CALL?

Q11. What is the LOCK prefix in 8086 and why is it used?

LOCK# is a bus signal that the 8086 asserts for one instruction, preventing any other bus master from accessing memory for the duration of that instruction, used to implement atomic read-modify-write operations in multiprocessor systems. In a two-processor shared-memory system with a semaphore at address 2000H, LOCK XCHG AX, [2000H] atomically swaps the semaphore without another processor interleaving between the read and write. Without LOCK, the read-modify-write is a three-bus-cycle sequence and another processor can modify the semaphore between the read and write cycles.

Follow-up: Which 8086 instructions can be used with the LOCK prefix?

Q12. What is the 8086 reset state?

On RESET, the 8086 sets CS to FFFFH, IP to 0000H, flags to 0, and clears DS, ES, and SS to 0000H, so the first instruction fetch comes from physical address FFFF0H. This address is typically the top of a ROM that holds a far jump instruction to the real startup code at a lower address. The 8086 does not clear general-purpose registers on reset, so code must never rely on register contents at startup before they are initialized.

Follow-up: Why is the reset vector placed at FFFF0H rather than at address 00000H like the 8085?

Q13. What is the difference between the 8086 and 8088?

The 8088 has the same 16-bit internal architecture as the 8086 but uses an 8-bit external data bus and a 4-byte prefetch queue instead of 6 bytes, making it cheaper to implement with 8-bit memory chips while sacrificing bus bandwidth. The IBM PC original used the 8088 specifically because 8-bit memory boards were cheaper and more available in 1981. For computation, the 8086 and 8088 execute identical instruction sets and produce identical results; only memory bandwidth and queue size differ.

Follow-up: Why did the IBM PC use the 8088 rather than the faster 8086?

Q14. What addressing modes does the 8086 support?

The 8086 supports register, immediate, direct (16-bit offset in instruction), register indirect ([BX], [SI], [DI], [BP]), based ([BX+disp], [BP+disp]), indexed ([SI+disp], [DI+disp]), and based indexed ([BX+SI+disp] etc.) addressing modes. The based indexed mode with displacement like MOV AX, [BX+SI+4] is the most powerful, allowing array element access where BX is the array base, SI is the index, and 4 is the field offset within a structure. This addressing flexibility directly influenced the design of later x86 processors.

Follow-up: Which base registers are allowed in 8086 memory addressing and which are not?

Q15. What is the role of the 8284 clock generator with the 8086?

The 8284A generates the CLK signal for the 8086 by dividing an external crystal frequency by 3, generates RESET from an RC network or power-on signal, and synchronizes the READY input from slow memories so it is properly timed relative to the bus cycle. The original 8086 ran at 5 MHz using a 15 MHz crystal with the 8284A dividing by 3; later versions ran at 8 and 10 MHz. The synchronization of READY is critical: an unsynchronized READY violates the metastability window of the 8086's internal latch and causes unpredictable behavior.

Follow-up: Why must the READY signal be synchronized to the 8086 clock rather than being connected directly from the memory chip?