Interview questions & answers
Q1. What is the 8255 PPI and what are its main features?
The 8255 is a Programmable Peripheral Interface IC that provides 24 I/O lines organized as three 8-bit ports (Port A, Port B, and Port C), each configurable as input or output under software control via a control word written to an internal register. A single 8255 replaces up to 24 discrete I/O buffers and eliminates the need for individual address decode logic for each I/O line. Its three operating modes — simple I/O, strobed I/O, and bidirectional handshake — make it suitable for everything from LED control to full bidirectional parallel printer interfaces.
Follow-up: How many address lines are needed to select between the three ports and the control register of the 8255?
Q2. What are the three modes of the 8255 and when would you use each?
Mode 0 (Basic I/O) configures each port as a simple input or output with no handshaking, suitable for LEDs, switches, and displays; Mode 1 (Strobed I/O) adds handshake signals using Port C bits so Port A or B can synchronize with a slow peripheral like a printer; Mode 2 (Bidirectional Bus) is available only for Port A and provides full bidirectional data transfer with handshaking, used for parallel bus connections between two processors. Mode 0 is used in 90% of student labs because most peripherals like the 7-segment display and keyboard matrix need no handshaking. Mode 2 is rarely implemented in practice due to the availability of faster serial interfaces.
Follow-up: Which port supports Mode 2 and which ports can only operate in Mode 0 or Mode 1?
Q3. How do you calculate the control word for the 8255?
The 8255 control word is an 8-bit value written to the control register: bit D7 must be 1 for mode set; bits D6–D5 set the mode for Group A (Port A); bit D4 sets Port A direction (1 = input); bit D3 sets Port C upper nibble direction; bit D2 sets Group B mode; bit D1 sets Port B direction; bit D0 sets Port C lower nibble direction. To configure Port A as output in Mode 0, Port B as input in Mode 0, and Port C as output entirely: the control word is 10000010B = 82H. Writing a wrong control word is the single most common cause of 8255 hardware failures in lab projects.
Follow-up: What is the control word to set all three ports as inputs in Mode 0?
Q4. What is the BSR mode of the 8255 and how does it differ from the I/O mode?
The BSR (Bit Set/Reset) mode is activated when bit D7 of the control word is 0 and allows individual bits of Port C to be set or cleared without affecting other bits, using a 4-bit field to select the bit and a 1-bit field to set or clear it. Writing 09H to the control register with D7=0 sets bit 4 of Port C high without disturbing bits 0–3 or 5–7. BSR mode is essential when Port C bits are used as individual device select or control lines that must be toggled independently in a shared-resource design.
Follow-up: Can BSR mode be used while Port C is configured for handshake lines in Mode 1?
Q5. What is the 8253 programmable interval timer and what are its main features?
The 8253 is a programmable timer/counter IC with three independent 16-bit down-counters (Counter 0, 1, 2), each capable of operating in six different modes at input clock rates up to 2 MHz, used for generating time delays, square waves, event counting, and baud rate generation. Intel originally designed Counter 0 of the 8253 to drive the system interrupt for the IBM PC timer tick at 18.2 Hz by dividing the 1.19 MHz clock by 65536. Its successor, the 8254, operates up to 8 MHz and adds a readback command to latch and read the counter value without disturbing timing.
Follow-up: What is the maximum count value of each 8253 counter?
Q6. What are the six operating modes of the 8253?
Mode 0 generates an interrupt on terminal count (output goes high after count reaches 0); Mode 1 is a hardware-triggered monostable (one-shot pulse); Mode 2 generates a periodic rate generator pulse (like a divide-by-N clock); Mode 3 generates a square wave with 50% duty cycle; Mode 4 is a software-triggered strobe; Mode 5 is a hardware-triggered strobe. Mode 3 is the most commonly used because it produces a clean square wave clock for baud rate generation, and Mode 0 is used for one-shot timing delays in 8085 systems. Mode 2 is used in PC timer chips to generate the 18.2 Hz system tick.
Follow-up: What is the difference between Mode 0 and Mode 4 in the 8253?
Q7. How do you write the control word for the 8253?
The 8253 control word is an 8-bit byte written to the control register: bits D7–D6 select the counter (00=Counter 0, 01=Counter 1, 10=Counter 2); bits D5–D4 select read/write mode (00=latch, 01=LSB only, 10=MSB only, 11=LSB then MSB); bits D3–D1 select the operating mode (000–101); bit D0 selects binary (0) or BCD (1) counting. To program Counter 0 in Mode 3 (square wave), read/write both bytes, binary counting: the control word is 00110110B = 36H. Forgetting to set D4–D5 to 11 (LSB then MSB) when loading a 16-bit count is the most common initialization error.
Follow-up: What happens if you write only the LSB of the count after programming the 8253 for LSB+MSB mode?
Q8. How is the 8255 connected to the 8085 bus?
The 8255 data pins D0–D7 connect directly to the 8085 multiplexed bus AD0–AD7 after demultiplexing by the 74LS373 latch; the two address pins A0 and A1 connect to address lines A1 and A2 (or through a decoder output); the chip select CS# is driven by a decoder output from the upper address lines; RD# and WR# connect directly to the 8085 RD# and WR# outputs; RESET connects to the 8085 RESET OUT pin. In a simple system with no other peripherals, CS# of the 8255 can be driven by A15 alone, placing Port A at 7FFCH and the control register at 7FFFH. Forgetting to connect RESET to the 8255 causes it to power up in an undefined mode.
Follow-up: Why is it important to write the control word to the 8255 before writing data to the ports?
Q9. What is the handshake mechanism in 8255 Mode 1?
In Mode 1, Port C provides the handshake signals: for Port A input, PC4 is the STB# (strobe from peripheral indicating data is ready), PC5 is IBF (input buffer full indicating the 8255 has latched the data), and PC3 is INTR (interrupt to the CPU that data is available); for Port A output, PC7 is OBF# (output buffer full indicating the CPU has loaded data), PC6 is ACK# (acknowledge from peripheral that it has taken the data), and PC3 is INTR. A parallel printer interface uses exactly this handshake: the CPU writes a byte, OBF# goes low, the printer reads it and pulses ACK#, which sets INTR to signal the CPU to load the next byte. Without handshaking, data bytes are lost when the peripheral cannot keep up.
Follow-up: What is the function of INTR in Mode 1 and how is it enabled?
Q10. How do you generate a 1 kHz square wave using the 8253?
Load Counter 0 in Mode 3 (square wave) with a count value of (input clock frequency / desired frequency): if the 8253 input clock is 2 MHz, the count value is 2000000 / 1000 = 2000 = 07D0H. Write the control word 36H (Counter 0, LSB+MSB, Mode 3, binary), then write 0D0H (LSB) and 07H (MSB) to the Counter 0 data port. The output pin GATE must be tied high and the OUT0 pin delivers the 1 kHz square wave, which can drive a buzzer, a baud rate clock, or trigger an interrupt at 1 ms intervals.
Follow-up: What would happen to the output if GATE is pulled low while the counter is running in Mode 3?
Q11. What is the difference between the 8253 and 8254?
The 8254 is an improved version of the 8253 with a higher maximum clock rate (10 MHz versus 2 MHz), a readback command that latches both the count and status register simultaneously without stopping the counter, and full CMOS compatibility. The readback command allows software to read the current counter value without the race condition that exists in the 8253 when reading a running counter with separate LSB and MSB reads. Most modern designs use the 8254 when an 8253-compatible timer is needed because the higher clock rate and readback capability make it more flexible.
Follow-up: What problem can occur when reading a running 16-bit counter value with two sequential byte reads?
Q12. How many I/O ports does the 8255 occupy in the 8085 address space?
The 8255 occupies 4 contiguous port addresses: Port A, Port B, Port C, and the Control Register, selected by the two address lines A0 and A1. If the base address is 00H, Port A is at 00H, Port B at 01H, Port C at 02H, and the control register at 03H. All four registers share a single chip select line, so a single AND gate or decoder output enables the entire 8255 as one 4-location block.
Follow-up: Can the 8255 ports be at non-contiguous addresses in the I/O map?
Q13. What is the purpose of the GATE input on the 8253 timer?
GATE controls counter operation: in Mode 0 and Mode 4 (software modes), GATE high enables counting and GATE low stops the counter; in Mode 1 and Mode 5 (hardware trigger modes), a rising edge on GATE triggers or re-triggers the one-shot; in Mode 2 and Mode 3, GATE low immediately disables the output and resets the counter, and a rising edge restarts it from the initial count. Connecting GATE to a flip-flop controlled by Port C of the 8255 allows the software to start and stop the timer precisely without writing a new count value. Leaving GATE unconnected (floating) in a TTL-level 8253 circuit results in intermittent counting because floating TTL inputs switch unpredictably.
Follow-up: What is the effect of a GATE rising edge on a counter running in Mode 2?
Q14. What initialization sequence is required to use the 8255 in Mode 1 for strobed input?
First, write the mode control word to the control register with D7=1 to activate mode set, Port A mode bits = 01 for Mode 1, Port A direction = 1 (input), and Port C upper bits configured for handshake; second, use BSR mode to set the INTE (interrupt enable) bit in Port C by setting PC4 via the BSR control word; third, enable interrupts in the 8085 with EI and SIM to unmask the relevant RST input connected to INTR. Skipping the INTE bit set step in the BSR write means INTR is never asserted even when data arrives, and the CPU polls forever.
Follow-up: Which Port C bit must be set via BSR to enable the interrupt output in Mode 1 for Port A input?
Q15. How does the 8253 operate in Mode 0 (interrupt on terminal count)?
In Mode 0, writing the control word and then the count value starts the counter; the OUT pin goes low immediately and stays low while the counter decrements; when the count reaches 0, OUT goes high and stays high until a new count is loaded. If the 8253 is clocked at 1 MHz and loaded with count 5000, the output goes high after exactly 5 ms, providing a one-shot hardware timeout. The output remains high after terminal count, so repeated timeouts require software to write a new count value each time — unlike Mode 2 which reloads automatically.
Follow-up: How would you use Mode 0 to measure the time between two external events?
Common misconceptions
Misconception: The 8255 control word bit D7 = 0 means the ports are configured as inputs.
Correct: Bit D7 = 0 activates BSR (Bit Set/Reset) mode for Port C; bit D7 must be 1 for any I/O mode configuration.
Misconception: The 8253 counter output goes high immediately when a count is written in Mode 3.
Correct: In Mode 3 (square wave), the counter must receive its first CLK edge after the count is loaded before it begins toggling; there is one CLK cycle of latency before output changes.
Misconception: Port C of the 8255 is always available for general I/O even in Mode 1.
Correct: In Mode 1, the upper nibble of Port C is used for Port A handshake signals and the lower nibble for Port B handshake signals, leaving no Port C bits free for general I/O.
Misconception: Writing the 8253 count as a single byte always sets the full 16-bit counter.
Correct: If the 8253 is programmed for LSB+MSB mode, only the LSB write takes effect until the MSB is written; an incomplete write leaves the counter in an undefined half-loaded state.