Interview questions & answers
Q1. What is the difference between a ripple counter and a synchronous counter?
In a ripple counter, each flip-flop is clocked by the output of the previous one, causing propagation delay that accumulates with each stage. A 4-bit 74HC93 ripple counter can have up to 4 gate delays before the output settles. Synchronous counters like the 74HC163 clock all flip-flops simultaneously, making them faster and glitch-free at higher frequencies.
Follow-up: At what frequency does ripple counter glitching become a real problem in practice?
Q2. How do you design a MOD-6 counter using a 74HC163?
You use the synchronous clear or load pin of the 74HC163 to force the counter back to zero when it reaches the count of 6 (binary 0110). Connect the QA and QB outputs through a NAND gate to the active-low clear pin so the counter resets at state 6 before reaching 7. This technique is used in BCD clock dividers where you need counts other than powers of two.
Follow-up: Why is it better to use synchronous clear instead of asynchronous clear in a MOD-6 counter?
Q3. What is a Johnson counter and how does it differ from a ring counter?
A Johnson counter feeds the inverted output of the last flip-flop back to the input of the first, producing 2N unique states from N flip-flops. A ring counter feeds the non-inverted output back, giving only N states. A 4-bit Johnson counter using four 74HC74 D flip-flops generates 8 distinct states, making it useful as a stepper motor sequencer.
Follow-up: What are the unused states in a Johnson counter and why do they matter?
Q4. What is the maximum count frequency of a ripple counter built from 74HC flip-flops?
The maximum clock frequency is limited by the total propagation delay across all stages: for a 4-bit ripple counter using 74HC flip-flops with 7 ns delay each, the worst-case settling time is 28 ns, limiting operation to around 35 MHz. In contrast, a synchronous 74HC163 can run at over 80 MHz because all stages switch together. This is why ripple counters are avoided in high-speed digital designs.
Follow-up: How would you calculate the maximum safe clock frequency for a 4-bit ripple counter?
Q5. How does a presettable counter work?
A presettable counter loads a predefined binary value into its flip-flops via parallel load pins when the load control signal is asserted, allowing counting to start from any value. The 74HC163 has a synchronous parallel load that activates on the clock edge, preventing glitches. This is used in UART baud rate generators where the counter must reload a specific divisor value every cycle.
Follow-up: What is the difference between synchronous load and asynchronous load in a presettable counter?
Q6. Explain how a decade counter (MOD-10) is implemented using the 74HC90.
The 74HC90 contains a divide-by-2 and a divide-by-5 section that can be cascaded internally by connecting QA to the B-clock input, producing a BCD count from 0 to 9 that resets on count 10. The reset inputs R0(1) and R0(2) are used to force reset to zero. This counter is directly used in digital clocks and frequency counters where decimal display is required.
Follow-up: How would you cascade two 74HC90 ICs to build a MOD-100 counter?
Q7. What is the role of the terminal count (TC) output in a 74HC163 counter?
The TC output goes high only when the counter reaches its maximum count (1111 for a 4-bit counter) and the count enable inputs are asserted, signaling downstream logic that the counter is about to roll over. It is used to enable the count of the next cascaded 74HC163 stage, allowing easy construction of 8-bit or 16-bit counters. Without TC, you would need external decode logic to detect rollover.
Follow-up: How does using TC for cascading differ from using a ripple carry output?
Q8. How would you build a frequency divider using a counter?
Connect the counter's terminal count output back to its synchronous load input and preload a value N; the output transitions once every (2^bits - N) input clock cycles, dividing the input frequency. A 74HC163 preloaded with 12 divides a 10 MHz clock by 4, producing a 2.5 MHz output. This technique is used in PLL reference dividers and clock generation circuits in microcontrollers.
Follow-up: What is the duty cycle of the output waveform from a counter-based frequency divider?
Q9. What is the difference between up counters, down counters, and up/down counters?
An up counter increments its count on each clock edge, a down counter decrements, and an up/down counter like the 74HC191 does either based on a direction control pin. The 74HC191 uses a single U/D pin: high for up-counting, low for down-counting. Up/down counters are used in motor control encoder interfaces where position is tracked in both directions of rotation.
Follow-up: What happens to the terminal count and borrow outputs when an up/down counter changes direction?
Q10. How do you detect a specific count in a counter circuit?
You decode the flip-flop outputs using logic gates that produce a pulse only when the desired binary combination is present on the output lines. For a MOD-12 counter needing detection at count 9 (1001), you AND Q3 and Q0 while Q2 and Q1 are low. This decoded output is used in traffic light sequencers and washing machine timer circuits to trigger state transitions.
Follow-up: How does using a NAND gate decoder reduce the propagation delay compared to an AND gate decoder?
Q11. What causes glitches in counter output decoding and how do you prevent them?
Glitches occur because flip-flop outputs do not all switch simultaneously, creating brief false logic combinations at the decoder output during transitions. In a ripple counter going from 0111 to 1000, intermediate states like 1110 or 1100 appear for nanoseconds. Using a synchronous counter like the 74HC163 and adding a latch on the decoder output clocked after settling time eliminates these glitches.
Follow-up: Why are glitches especially problematic when the decoded counter output drives a one-shot or interrupt input?
Q12. What is a gray code counter and why is it used?
A gray code counter produces output sequences where only one bit changes between consecutive counts, eliminating the multi-bit transition glitches that cause errors in position sensing systems. An optical shaft encoder outputs gray code so that mechanical jitter at a transition boundary only reads one step of error rather than wildly incorrect positions. Gray code counters are standard in absolute rotary encoders used in industrial servo drives.
Follow-up: How do you convert a binary counter output to gray code using XOR gates?
Q13. How does a counter-based PWM generator work?
A free-running counter is compared against a programmable compare register; the PWM output is set high when the counter resets and cleared when the counter value matches the compare register value, producing a duty cycle proportional to the compare value. In the ATmega328, Timer1 running at 16 MHz with a 16-bit counter can generate PWM frequencies down to 244 Hz with 16-bit resolution. This is the fundamental operating principle of all hardware PWM modules in microcontrollers.
Follow-up: How do you change PWM frequency without affecting the duty cycle resolution in a counter-based PWM?
Q14. What is the modulus of a counter and how do you calculate it?
The modulus is the total number of unique states the counter passes through before recycling; an n-bit binary counter has a natural modulus of 2^n, while a MOD-N counter is forced to recycle after N states. A 4-bit counter has modulus 16 naturally, but inserting a decode-and-reset at count 10 gives a decade counter with modulus 10. Modulus directly equals the division ratio when the counter is used as a frequency divider.
Follow-up: How does the modulus of a counter affect the output waveform symmetry?
Q15. How are counters used in a digital stopwatch circuit?
A 32.768 kHz crystal oscillator is divided down to 1 Hz using a chain of MOD-2 counters (15 stages), then fed into cascaded decade counters to accumulate seconds, tens of seconds, minutes, and tens of minutes, with each decade counter driving a BCD-to-7-segment decoder. The 74HC4060 provides 14 stages of binary division from the crystal directly on one chip. This architecture is used in every battery-powered RTC and wristwatch IC.
Follow-up: Why is a 32.768 kHz crystal specifically chosen for timekeeping applications?
Common misconceptions
Misconception: A ripple counter's maximum frequency is limited only by the flip-flop's clock-to-Q delay.
Correct: The maximum frequency is limited by the cumulative propagation delay across all stages, not just one flip-flop, because each stage clocks the next.
Misconception: A MOD-10 counter and a decade counter are different things.
Correct: They are the same thing; both refer to a counter with 10 states (0 through 9) that resets on the 10th count.
Misconception: The terminal count output of a 74HC163 pulses high for one full clock cycle at every count value.
Correct: The TC output is high only when the counter is at its maximum count (1111) and count-enable inputs are both asserted, not at every count.
Misconception: Adding more bits to a ripple counter always allows higher frequency operation.
Correct: More stages in a ripple counter increase total propagation delay, making it slower, not faster.