Flip-Flop Interview Questions

Q1. What is a flip-flop and how does it differ from a latch?

A flip-flop is an edge-triggered bistable circuit that changes state only on the rising or falling edge of a clock signal, while a latch is level-sensitive — it changes output when the enable/clock is at a certain level (transparent). The 74HC74 D flip-flop captures input D only on the rising clock edge, ignoring D between edges; the 74HC373 D latch passes D to Q whenever Enable is high (transparent). Flip-flops are used in synchronous sequential circuits (registers, counters, state machines) where controlled timing is critical, while latches are used in address bus hold circuits and some multibit sampling applications.

Follow-up: What problem with latches is solved by using edge-triggered flip-flops?

Q2. Explain the operation of an SR flip-flop and what is the forbidden state?

An SR flip-flop has Set (S) and Reset (R) inputs: S=1,R=0 → Q=1 (set state); S=0,R=1 → Q=0 (reset state); S=0,R=0 → Q unchanged (memory state). The forbidden state is S=1,R=1 — both outputs Q and Q' become 1 simultaneously, violating the complementary relationship, and when S and R return to 00, the state is indeterminate (either output may settle to 1 depending on gate delays). In practice, SR latches built from NAND gates (as in the 74HC00) have the forbidden condition at S=0,R=0 (both inputs low) because NAND gates invert the active condition.

Follow-up: How do you eliminate the forbidden state in an SR flip-flop to create a D flip-flop?

Q3. Explain the working of a D flip-flop and list its applications.

A D (Data or Delay) flip-flop captures the value of input D on the active clock edge and holds it at output Q until the next clock edge, effectively implementing a 1-bit memory element with no forbidden states. The 74HC74 D flip-flop with asynchronous preset (PRE') and clear (CLR') captures D on the rising clock edge: if D=1 before the rising edge, Q goes to 1 after the edge regardless of what happens to D afterward. Applications: data registers (74HC374 = 8 D flip-flops for data bus latching), frequency dividers (Q connected back to D' for divide-by-2), and pipeline registers in RISC-V processor datapaths where each stage register is an array of D flip-flops.

Follow-up: How does connecting Q' back to D convert a D flip-flop into a toggle flip-flop?

Q4. Explain the JK flip-flop and how it eliminates the forbidden state of the SR flip-flop.

The JK flip-flop is like an SR flip-flop but redefines the J=1, K=1 condition: instead of forbidden, it causes the flip-flop to toggle (Q changes to Q'). J=1,K=0 → Set; J=0,K=1 → Reset; J=0,K=0 → Hold; J=1,K=1 → Toggle. The 74HC112 negative-edge-triggered JK flip-flop with J=K=1 and 1 MHz clock produces a 500 kHz toggle output on Q, making it ideal as a frequency divider. The JK is the most versatile flip-flop — it can implement D type (K=J'), T type (J=K=T), and SR type (K=R, J=S) by connecting inputs appropriately.

Follow-up: How do you convert a JK flip-flop into a T flip-flop?

Q5. What is a T flip-flop and what is its primary application?

A T (Toggle) flip-flop changes state (Q → Q') on every active clock edge when T=1, and holds state when T=0; it is implemented as a JK flip-flop with J=K=T or a D flip-flop with D=Q'. The primary application is binary counting: a chain of T flip-flops with T permanently tied high creates a ripple counter (asynchronous counter) where each stage divides the clock by 2. A 4-stage ripple counter using 74HC112 JK flip-flops with J=K=VCC counts from 0 to 15 (modulo-16), with Q0 = clock/2, Q1 = clock/4, Q2 = clock/8, Q3 = clock/16.

Follow-up: What is the main limitation of a ripple counter compared to a synchronous counter?

Q6. What is the difference between a synchronous and asynchronous counter?

In an asynchronous (ripple) counter, each flip-flop is clocked by the output of the previous stage, so clock signals propagate sequentially — the final stage's output is delayed by N×tpd where N is the number of stages and tpd is the flip-flop propagation delay. In a synchronous counter, all flip-flops share the same clock and change simultaneously, with the combinational logic determining next-state inputs computed in parallel. A 4-bit 74HC163 synchronous counter has maximum counting frequency >100 MHz with all four bits changing simultaneously; a 4-bit ripple counter using 74HC112 has maximum frequency limited to ~35 MHz due to accumulated 4×7ns = 28 ns delay, plus glitch states on the output during ripple propagation.

Follow-up: What are glitch states in a ripple counter and why do they cause problems?

Q7. What are setup time and hold time in a flip-flop and what happens if violated?

Setup time (tsu) is the minimum time the D input must be stable before the active clock edge; hold time (th) is the minimum time D must remain stable after the clock edge. The 74HC74 specifies tsu = 20 ns and th = 3 ns at 5 V, 25°C. Violating setup time causes the flip-flop to enter a metastable state — an undefined output between 0 and 1 that can persist for an unpredictable duration before resolving, causing timing failures in synchronous systems. This is why synchronizers (two flip-flops in series) are used at clock domain crossing boundaries in SoC designs, allowing enough time for metastability to resolve before the second flip-flop samples.

Follow-up: What is metastability and how is it handled in clock domain crossing circuits?

Q8. How do you design a 3-bit synchronous counter using JK flip-flops?

For a modulo-8 up counter with states 000 to 111, derive J/K excitation equations from the state transition table: JA=KA=1, JB=KB=QA, JC=KC=QAQB (standard binary count excitation). Implement: FA uses J=K=1 (always toggles); FB uses J=K=QA (toggles when QA=1); FC uses J=K=QAQB (toggles when both QA and QB are 1). Wire three 74HC112 JK flip-flops with these inputs, connect all CLK pins to the same clock — the design counts 000, 001, 010, 011, 100, 101, 110, 111 synchronously with all transitions happening simultaneously at the clock edge.

Follow-up: How would you modify this counter to count from 000 to 101 (modulo-6)?

Q9. What is a shift register and what are its applications?

A shift register is a chain of D flip-flops where each stage's Q output connects to the next stage's D input, so data shifts one position on each clock edge — the 74HC595 8-bit serial-in parallel-out (SIPO) shift register is used to expand a microcontroller's output ports over a 3-wire SPI interface. A 4-bit shift register clocked at 1 MHz shifts 4-bit data in from a serial line at 1 Mbps and makes all bits available in parallel after 4 clock cycles. Applications: serial-to-parallel conversion (SPI/UART receive), parallel-to-serial conversion (SPI transmit), time delay elements in DSP (FIFO buffers), and pseudo-random bit sequence (PRBS) generators using linear feedback shift registers (LFSR).

Follow-up: What is a linear feedback shift register (LFSR) and what is it used for?

Q10. What is clock skew and how does it affect flip-flop timing?

Clock skew is the difference in clock signal arrival time at different flip-flops in a synchronous circuit, caused by unequal PCB trace lengths, buffer delays, or via parasitics. In a 74HC74-based 100 MHz counter with 2 ns skew between flip-flop clocks, the effective setup time budget at the receiving flip-flop reduces by 2 ns — if tsu = 3 ns and cycle time = 10 ns, the maximum propagation delay between stages is limited to 10 - 3 - 2 = 5 ns. Positive clock skew (clock arrives later at capturing flip-flop) helps timing; negative skew tightens hold time requirements and can cause hold violations. ASIC layout tools like Synopsys IC Compiler perform clock tree synthesis to minimize and balance skew.

Follow-up: What is hold time violation and how is it different from setup time violation?

Q11. Explain the master-slave JK flip-flop and why it was used historically.

A master-slave JK flip-flop consists of two SR latches in series: the master latch is transparent on the clock's high phase and the slave latch is transparent on the low phase, so data captured from J, K during clock=1 is transferred to the output only when clock goes low — creating an effectively edge-triggered device from level-sensitive latches. The 7476 IC was a master-slave JK flip-flop widely used in 1970s–1980s TTL logic, but it suffered from '1s catching' — any glitch on J while clock is high would be captured even if J was low before the clock rising edge. Modern flip-flops like the 74HC112 use true edge-triggered CMOS circuitry that only samples inputs in a tiny window around the clock edge, completely eliminating 1s catching.

Follow-up: What is 1s catching in a master-slave flip-flop and why does it cause design problems?

Q12. What is a Johnson counter and how does it differ from a binary ripple counter?

A Johnson (twisted ring) counter connects the Q' output of the last flip-flop back to the D input of the first, generating a unique sequence of 2N states (vs N states for a ring counter and 2^N for binary) with only N flip-flops and no decoding glitches. A 4-bit Johnson counter using the 74HC164 produces 8 unique states: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 — each state differs from the next by only one bit, which eliminates glitches when decoding outputs. Johnson counters are used in clock dividers, phase generators for motor control (3-phase PWM sequencers in stepper drivers), and ring oscillator-based frequency synthesizers.

Follow-up: How many states does a 4-bit Johnson counter produce and what is the sequence?

Q13. What is the function of the asynchronous preset (PRE) and clear (CLR) inputs of a flip-flop?

Asynchronous PRE (preset, active-low PRE' in 74HC74) forces Q to 1 regardless of clock or D input when asserted; asynchronous CLR (clear) forces Q to 0 regardless of clock. In the 74HC74, asserting PRE' = 0 immediately forces Q = 1 and Q' = 0 — no clock edge is needed — making these inputs useful for power-on reset circuits that initialize the digital system to a known state before the clock starts. Asserting both PRE' and CLR' simultaneously is forbidden (same as SR flip-flop's forbidden state), producing Q = Q' = 1 which is an invalid state for the flip-flop.

Follow-up: How is a system-wide reset circuit designed using the CLR input of all flip-flops?

Q14. What is a state machine and how are its flip-flop equations derived?

A finite state machine (FSM) is a sequential circuit with a finite number of states, transition conditions, and outputs defined by a state transition diagram; flip-flop excitation equations are derived by filling a state table, mapping next-state bits to flip-flop inputs using excitation tables (for JK or SR types) or directly (for D type), then minimizing using K-maps. A Moore-type traffic light controller with 3 states (Red=00, Green=01, Yellow=10) using two 74HC74 D flip-flops needs D1 = Q1'Q0 (transition to Yellow from Green) and D0 = Q1'Q0' (transition to Green from Red), derived from the state transition table. All sequential circuit design reduces to this process: state diagram → state table → excitation equations → K-map minimization → gate/flip-flop implementation.

Follow-up: What is the difference between Moore and Mealy state machines?

Q15. Explain race condition and hazard in sequential circuits.

A race condition occurs in asynchronous sequential circuits when two or more state variables must change simultaneously — the final state depends on which flip-flop wins the 'race' to change first, causing non-deterministic behavior. A critical race in a state transition from 00 to 11 via either 01 or 10 may settle in either intermediate state depending on propagation delay differences. In synchronous circuits, clock edge alignment eliminates races by ensuring all transitions occur simultaneously; the 74HC163 synchronous counter avoids the glitch states of a ripple counter precisely because all four flip-flops change at the same clock edge, preventing any race conditions.

Follow-up: What is an asynchronous sequential circuit and why are they rarely used compared to synchronous designs?