Shift Register Interview Questions

Q1. What are the four operating modes of a shift register?

The four modes are Serial-In Serial-Out (SISO), Serial-In Parallel-Out (SIPO), Parallel-In Serial-Out (PISO), and Parallel-In Parallel-Out (PIPO). The 74HC595 operates as SIPO, accepting serial data on its DS pin and presenting all 8 bits simultaneously on its output latches. Knowing which mode you need before selecting a shift register IC saves significant PCB redesign time.

Follow-up: For what application would you specifically choose a PISO shift register over a SIPO?

Q2. How does the 74HC595 shift register work and where is it commonly used?

The 74HC595 is an 8-bit SIPO shift register with an output latch; data is clocked in serially on the SRCLK pin and then transferred simultaneously to the output pins when the RCLK (latch clock) is pulsed. Three microcontroller GPIO pins can control 8 LEDs without flickering because the latch holds the last byte while new data shifts in. Chaining multiple 74HC595 ICs over a single SPI line is standard practice in LED matrix and 7-segment multiplexed displays.

Follow-up: What happens to the output pins of the 74HC595 while new data is being shifted in?

Q3. What is the difference between a shift register and a counter?

A shift register moves stored bits laterally from stage to stage on each clock pulse, while a counter increments or decrements a binary value by toggling flip-flop states through carry logic. A 74HC595 shifts an 8-bit word one position right each clock cycle, whereas a 74HC163 adds 1 to its stored binary count. Both are built from flip-flops, but their feedback structure determines whether they shift or count.

Follow-up: Can a shift register be configured to act as a counter? What type?

Q4. How do you implement a serial-to-parallel conversion using a shift register?

Clock the serial data bit-by-bit into the shift register's serial input, one bit per clock cycle, until all bits are loaded; then latch or read the parallel outputs simultaneously. An SPI ADC like the MCP3204 sends its 12-bit result serially, and a 74HC595 connected to an MCU's SPI bus reconstructs the parallel word for further processing. This serial-to-parallel approach reduces wiring from N lines to 3 SPI lines regardless of word length.

Follow-up: How many clock pulses does it take to fully load an 8-bit shift register serially?

Q5. What is a universal shift register?

A universal shift register supports all four modes — SISO, SIPO, PISO, and PIPO — selectable via mode control pins, and can shift data both left and right. The 74HC194 is a 4-bit universal shift register with S0 and S1 select pins that choose the operating mode. It is used in arithmetic logic units to implement logical shift and rotate operations on operands.

Follow-up: What are the S0 and S1 pin states on a 74HC194 to select left-shift mode?

Q6. How is a shift register used in a UART transmitter?

The UART loads the 8-bit parallel data byte into a shift register, then serially clocks out each bit at the baud rate — LSB first — preceded by a start bit and followed by a stop bit. A 16550 UART IC uses exactly this transmit shift register architecture, with the baud rate generator setting the clock frequency. The start and stop bits are appended in hardware so the CPU only writes the data byte to a transmit buffer register.

Follow-up: Why does UART transmit the LSB first rather than the MSB first?

Q7. What is a linear feedback shift register (LFSR) and what is it used for?

An LFSR is a shift register where the input to the first stage is a XOR combination of selected output stages called taps, producing a pseudorandom binary sequence before repeating. A 16-bit LFSR with taps at positions 16 and 15 generates a maximal-length sequence of 65,535 bits before repeating. LFSRs are used for pseudorandom number generation in spread-spectrum communications, built-in self-test (BIST) circuits in VLSI, and CRC generation.

Follow-up: What determines the period length of an LFSR sequence?

Q8. How do you daisy-chain multiple 74HC595 ICs to drive a 16-bit output from 3 MCU pins?

Connect the Q7' serial output of the first 74HC595 to the serial data input of the second, share the SRCLK and RCLK signals between both chips, and shift out 16 bits total before pulsing RCLK once to latch both devices simultaneously. An Arduino driving two chained 74HC595s uses exactly this method to control 16 stepper motor phase outputs using only the SPI pins. This scalability to N devices on the same 3 wires is why the 74HC595 is the standard solution for GPIO expansion.

Follow-up: What is the maximum number of 74HC595 ICs you can daisy-chain before signal integrity becomes a concern?

Q9. What is the purpose of the output enable (OE) pin on a 74HC595?

The active-low OE pin tri-states all eight output pins when pulled high, disconnecting them from the bus without disturbing the data latched in the storage register. Pulling OE high lets you preload new data into the shift register while the outputs are driving something else, then re-enable outputs with a single pin toggle. This is used in bus arbitration circuits where multiple 74HC595 drivers share an output bus.

Follow-up: Does toggling the OE pin affect the data already stored in the 74HC595's latch register?

Q10. What is the difference between the shift register clock and the latch clock in a 74HC595?

The shift register clock (SRCLK) moves data through the internal flip-flop chain one bit at a time, while the latch clock (RCLK) transfers the entire contents of the shift register to the output storage register simultaneously. This two-clock architecture means the outputs remain stable while new data is being shifted in, preventing glitches on the output pins during data loading. Without the separate latch clock, each output pin would change state as each bit shifts through.

Follow-up: What output behavior would you observe on a 74HC595 if you connected SRCLK and RCLK to the same clock signal?

Q11. How is a shift register used in SPI communication?

SPI uses shift registers in both master and slave devices; on every SCLK pulse, the master shifts out one bit on MOSI while simultaneously shifting in one bit on MISO, effectively exchanging the entire contents of both shift registers after N clocks. The STM32 SPI peripheral internally implements an 8-bit or 16-bit shift register that feeds the SPI data register. Full-duplex data exchange in SPI is a direct consequence of this shift-register-exchange architecture.

Follow-up: What is the significance of CPOL and CPHA settings in relation to when the shift register captures and drives data?

Q12. What is recirculating mode in a shift register?

Recirculating mode connects the serial output of the last stage back to the serial input of the first stage, so the stored bit pattern rotates continuously without being lost. A 4-bit shift register in recirculate mode storing 1000 will cycle through 1000, 0100, 0010, 0001, 1000 indefinitely. This is used in ring counter-based stepper motor drive sequencers and round-robin arbitration circuits in digital systems.

Follow-up: How many unique states does a 4-bit recirculating shift register with initial value 0001 produce?

Q13. What is the propagation delay concern when cascading many shift register stages?

Each shift register stage adds its clock-to-Q propagation delay to the data path, and the setup time of the next stage must be met after the last stage in the chain settles. For a 74HC595 with 13 ns clock-to-Q delay at 5V, chaining 8 devices imposes a cumulative serial data path delay that limits maximum clock frequency before hold-time violations occur. In PCB design, this is why long shift register chains use buffered clock signals and have a maximum specified clock frequency.

Follow-up: How does supply voltage affect the maximum clock frequency of a cascaded 74HC595 chain?

Q14. How do you use a PISO shift register to read multiple switch inputs using only 3 MCU pins?

Load the switch states in parallel into the PISO shift register by asserting the parallel load pin, then clock out all 8 bits serially into the MCU's SPI receive buffer. The 74HC165 accepts 8 switch inputs in parallel and delivers them serially on its QH pin, requiring only SH/LD, CLK, and QH pins connected to the MCU. This multiplexing technique is used in mechanical keyboard matrix controllers and industrial panel button readers.

Follow-up: How do you synchronize the parallel load pulse of a 74HC165 with the MCU's SPI clock?

Q15. What is a bucket brigade and how does it relate to shift registers?

A bucket brigade device (BBD) is an analog shift register where charge packets representing analog voltage samples pass from one capacitor stage to the next on each clock pulse, delaying the signal by N clock periods. The MN3007 is a 1024-stage BBD used in analog audio chorus and flanger effects pedals to produce comb filtering delays. Unlike digital shift registers that store logic bits, BBDs preserve analog amplitude information through the delay chain.

Follow-up: What limits the audio quality of a bucket brigade device compared to a digital delay implemented with RAM?