Logic Gates Interview Questions

Q1. What are the basic logic gates and their Boolean expressions?

The basic logic gates are AND (Y = A·B, output high only when all inputs are high), OR (Y = A+B, output high when any input is high), NOT (Y = A', output inverts input), NAND (Y = (A·B)'), NOR (Y = (A+B)'), XOR (Y = A⊕B = A'B + AB', output high when inputs differ), and XNOR (Y = (A⊕B)', output high when inputs are equal). In a 74HC08 quad 2-input AND gate operating at 5 V, the output goes to logic high (~4.9 V) only when both inputs are above the logic-1 threshold (~3.5 V for HC family). Understanding these seven gates and their truth tables is the foundation for all combinational and sequential digital design.

Follow-up: Why is NAND considered more fundamental than AND in practical digital design?

Q2. Why are NAND and NOR called universal gates?

NAND and NOR are universal because any other logic function — AND, OR, NOT, XOR, or any combinational circuit — can be implemented using only NAND or only NOR gates, making them sufficient alone for any digital design. A NOT gate using NAND: tie both inputs together (A NAND A = A'). AND using NAND: NAND followed by a NAND-NOT inverter. In the 74HC00 quad NAND package, all six standard logic functions can be realized. NAND universality is why early ICs like the 7400 NAND gate became the building block of entire computer systems — one gate type minimized inventory and production complexity.

Follow-up: How do you implement an OR gate using only NAND gates?

Q3. Explain the working of an XOR gate and list three of its applications.

An XOR gate outputs high (1) when its inputs are different and low (0) when inputs are the same: Y = A⊕B = A'B + AB'. The 74HC86 XOR operates at 5 V with propagation delay ~7 ns. Applications: (1) Parity generator/checker in UART communication — XOR of all data bits gives even parity bit; (2) Half adder — the sum bit of 1-bit addition is A XOR B while carry is A AND B; (3) Comparator — A XOR B = 0 only when A = B, used to detect if two digital values are equal. XOR is also the core operation in hardware encryption (XOR cipher and AES mix columns).

Follow-up: How does an XNOR gate differ from XOR and what is its main application?

Q4. What is fan-out in digital logic and what happens if it is exceeded?

Fan-out is the maximum number of gate inputs a single output can drive while maintaining valid logic levels, determined by the ratio of the driving gate's output current capacity to the input current requirement of each driven gate. A 74HC04 inverter can source/sink 25 mA, and each 74HC gate input requires only 1 µA, so fan-out for HC-to-HC driving is >1000; but driving 74LS inputs that require 0.4 mA each limits fan-out to ~60. Exceeding fan-out causes the output voltage to fall (for high output) or rise (for low output) outside the valid logic level range, causing the driven gates to interpret the signal incorrectly and causing unpredictable circuit behavior.

Follow-up: How do you drive a large fan-out requirement in a practical PCB design?

Q5. What is propagation delay in a logic gate and how does it affect circuit timing?

Propagation delay (tpd) is the time from the input signal transition to the corresponding output change, measured from the 50% points of each waveform transition. The 74HC00 NAND has tpd = 7 ns typical at 5 V, while the 74AHC00 achieves tpd = 3.5 ns; in contrast, the CD4011 CMOS NAND has tpd = 100 ns. In a ripple counter built with 74HC74 flip-flops where each stage has 7 ns delay, a 16-stage counter accumulates 112 ns of propagation delay from input to final output, limiting its maximum clock frequency to <9 MHz despite each flip-flop being specifiable at higher frequencies.

Follow-up: What is the difference between tPHL and tPLH, and why might they differ?

Q6. What is noise margin in a digital logic gate and how is it calculated?

Noise margin is the tolerable voltage noise on a logic signal before it is misinterpreted, calculated as: NMH = VOH_min - VIH_min (high-state noise margin) and NML = VIL_max - VOL_max (low-state noise margin). For 74HC logic at 5 V: VOH_min = 4.4 V, VIH_min = 3.5 V, VOL_max = 0.1 V, VIL_max = 1.0 V → NMH = 0.9 V, NML = 0.9 V. In industrial environments at ABB where VFDs generate significant electrical noise, choosing HC-family gates with 0.9 V noise margin instead of 74LS (NM ≈ 0.3 V) provides 3× better immunity to induced noise on PCB traces.

Follow-up: Why does 74HC logic have better noise margin than 74LS logic?

Q7. How is a NAND gate implemented in CMOS technology?

A CMOS 2-input NAND uses two PMOS transistors in parallel (source to VDD, drains tied to output) and two NMOS in series (source of second NMOS to GND) with each input controlling one PMOS and one NMOS. When both inputs are high, both NMOS are on (series path to GND) and both PMOS are off, pulling output low; any input low turns on its PMOS (parallel path to VDD) and breaks the NMOS series path, pulling output high. In a 65 nm CMOS standard cell library, a 2-input NAND gate occupies about 0.5 µm² and consumes only leakage power in static states — enabling billions of such gates on a single SoC.

Follow-up: Why is NAND preferred over AND as a basic building block in CMOS standard cell libraries?

Q8. What is the difference between TTL and CMOS logic families in terms of power and speed?

TTL (74xx series) uses BJTs and draws constant quiescent current (~10 mA for 7400), giving low propagation delay (~10 ns for 74AS) but significant static power dissipation that scales with gate count. CMOS (74HCxx, 74ACxx) draws essentially zero quiescent current but dynamic power proportional to f×C×VDD², making CMOS power increase with clock frequency while TTL power is constant. The 74HC00 at 1 MHz draws ~1 mW while the 7400 draws ~50 mW at the same logic function — which is why all modern digital ICs are CMOS: at 3 GHz clock rates, CMOS's frequency-proportional power is still manageable, while TTL's constant current would make billion-transistor chips thermally impossible.

Follow-up: What happens to CMOS power dissipation as clock frequency increases?

Q9. How do you implement a 4-input AND gate using 2-input AND gates?

A 4-input AND is implemented as a tree of three 2-input AND gates: Y = A·B·C·D = ((A·B)·(C·D)), where the first level computes A·B and C·D in parallel (2 gates), and the second level ANDs these intermediate results (1 gate). Using 74HC08 quad 2-input AND gates, three gates from a single IC implement the 4-input AND function with total propagation delay of 2 × tpd = 14 ns. This tree structure is always preferred over a chain (((A·B)·C)·D) in timing-critical paths because it halves the propagation delay at the same gate count — a key principle in synthesized digital logic optimization.

Follow-up: What is the critical path in a digital circuit and how does gate tree structure affect it?

Q10. What is a tri-state buffer and when is it used?

A tri-state buffer has three output states: logic high, logic low, and high-impedance (Hi-Z), where the high-impedance state effectively disconnects the output from the bus, allowing multiple drivers to share a common wire without conflict. The 74HC125 quad tri-state buffer enables each output only when its OE (output enable) pin is low; when OE is high, the output floats to Hi-Z. In a microprocessor data bus where ROM, RAM, and peripheral ICs all need to drive the same 8 lines, tri-state buffers ensure only one device drives the bus at a time, with all others in Hi-Z — the fundamental mechanism of shared data bus architecture.

Follow-up: What is bus contention and what damage can it cause?

Q11. What is a logic level translator and why is it needed?

A logic level translator converts signals between different logic voltage standards — for example, between a 3.3 V microcontroller (STM32) and a 5 V peripheral (Arduino shield), where the 3.3 V output (~3.1 V minimum) may not reliably drive a 5 V input requiring VIH > 3.5 V. The BSS138 NMOS-based bidirectional level translator or the TXS0108E IC translate between 1.2 V–3.6 V and 1.65 V–5.5 V systems with tpd < 4 ns. Without level translation, I2C lines between a 3.3 V ESP32 and a 5 V LCD may appear as 'low' to the LCD, causing communication failure or, worse, the 5 V output back-feeding into the 3.3 V GPIO and permanently damaging the STM32.

Follow-up: What is the difference between a unidirectional and bidirectional level translator?

Q12. Explain the concept of positive and negative logic conventions.

In positive logic, the higher voltage level represents logic 1 (true) and lower voltage level represents logic 0 (false); in negative logic, it is the reverse — lower voltage = 1, higher voltage = 0. A 74HC08 AND gate in positive logic (VDD=5V: 5V=1, 0V=0) performs AND: Y=A·B. The same physical gate in negative logic convention performs OR: Y=A+B (because physically NAND behavior maps to OR in negative logic by De Morgan's theorem). Modern digital design exclusively uses positive logic convention, but understanding negative logic is essential when reading older datasheets from the 1970s–1980s that specified 74-series gates in both conventions.

Follow-up: How does De Morgan's theorem relate positive-logic NAND to negative-logic NOR?

Q13. What is a Schmitt trigger input and why is it used in digital logic circuits?

A Schmitt trigger input has two different threshold voltages (VT+ and VT-) for rising and falling signals, providing hysteresis that prevents multiple output transitions from slow or noisy input signals. The 74HC14 hex inverting Schmitt trigger has VT+ = 2.4 V and VT- = 1.2 V at 5 V supply, giving 1.2 V hysteresis. Using a 74HC14 as the input stage for a mechanical switch eliminates contact bounce — even though the switch contact bounces between 0 V and 3 V many times during closing, the hysteresis ensures clean single-edge transitions in the debounced output, preventing false triggering of counters and flip-flops.

Follow-up: How does the hysteresis band of a Schmitt trigger affect its noise immunity?

Q14. What is wired-AND and in which logic family is it possible?

Wired-AND means multiple gate outputs are connected together on the same wire, and the combined output is the AND of all individual outputs — this requires open-collector (or open-drain) outputs so that any gate pulling its output low drives the shared line low, and the line goes high only when no gate pulls low. The 74HC03 quad NAND with open-collector outputs connected to a common 4.7 kΩ pull-up resistor on an I2C bus implements wired-AND, allowing both master and slave to pull SDA low without bus contention. Standard totem-pole TTL or CMOS outputs cannot be wired together because conflicting outputs (one driving high, another driving low) create a low-resistance short that burns out the output transistors.

Follow-up: Why is wired-AND used on the I2C bus?

Q15. How does the number of inputs affect the propagation delay and power of a CMOS gate?

In CMOS, increasing the number of inputs in a NAND or NOR gate adds more series NMOS (for NAND) or series PMOS (for NOR) transistors in the pull-down/pull-up path, increasing the effective channel resistance and hence propagation delay — a 4-input CMOS NAND is roughly 2× slower than a 2-input NAND. Input capacitance scales directly with transistor count, increasing dynamic power. A 74HC30 8-input NAND has tpd = 13 ns at 5 V compared to 7 ns for the 74HC00 2-input NAND for this reason. This is why wide gate implementations are decomposed into 2- or 3-input gate trees in CMOS synthesis to balance speed and area.

Follow-up: Why are 2-input gates preferred over multi-input gates in standard cell design?