Logic Families Interview Questions

Q1. What are the key electrical differences between TTL and CMOS logic families?

TTL uses bipolar junction transistors and draws significant quiescent current even in static states, with logic levels defined as VOH ≥ 2.4V and VOL ≤ 0.4V on a 5V supply, while CMOS uses complementary MOSFETs that draw near-zero static current with logic levels scaling with supply voltage (typically VOH = VDD − 0.1V, VOL = 0.1V). A 74LS00 NAND gate draws about 2 mA quiescent current from the 5V supply, whereas a 74HC00 in the same topology draws under 1 µA. This power difference is why CMOS replaced TTL in battery-operated and high-density applications.

Follow-up: How does operating frequency affect the dynamic power consumption of a CMOS gate versus a TTL gate?

Q2. What is noise margin and how is it calculated for the 74HC logic family?

Noise margin is the voltage difference between the guaranteed output level and the minimum acceptable input threshold, representing how much noise a logic signal can tolerate without causing an incorrect output. For 74HC at 5V, the low noise margin = VIL(max) − VOL(max) = 1.5V − 0.1V = 1.4V and the high noise margin = VOH(min) − VIH(min) = 4.9V − 3.5V = 1.4V. A larger noise margin makes a circuit more tolerant of ground bounce, power supply ripple, and capacitive coupling from adjacent PCB traces.

Follow-up: How does reducing supply voltage from 5V to 3.3V affect the noise margin of a 74LVC gate?

Q3. What is fan-out in logic gates and what limits it?

Fan-out is the maximum number of inputs of the same logic family a single gate output can drive while maintaining valid logic levels; it is limited by the output current sourcing/sinking capability versus the total input current demanded. A 74LS gate can sink 8 mA at VOL and each 74LS input requires 1.6 mA, giving a fan-out of 5 within the LS family. Exceeding fan-out causes the output voltage to drift into the undefined region, causing intermittent logic errors that are difficult to debug.

Follow-up: How do CMOS logic families achieve much higher fan-out numbers than TTL families?

Q4. What is propagation delay and how does it differ between 74LS and 74HC?

Propagation delay is the time from a logic input transition to the resulting output transition, measured at 50% of both waveforms. A 74LS00 has a typical propagation delay of 9 ns, while a 74HC00 is typically 7 ns at 5V, making them comparable in speed but the HC family becomes faster at lower supply voltages for its class. 74LS is faster than older 74L but slower than 74ALS (3 ns) or 74AC (5 ns), and selecting the right subfamily prevents clock skew in synchronous digital designs.

Follow-up: How does propagation delay vary with supply voltage in CMOS gates and what does this imply for 3.3V system design?

Q5. What is ECL (Emitter-Coupled Logic) and what applications justify its use?

ECL uses differential emitter-coupled bipolar transistors that never enter saturation, enabling propagation delays under 1 ns at the cost of very high power dissipation of 25–50 mW per gate and negative supply voltages (−5.2V typical for 10K ECL). Motorola MECL 10K series gates achieve 1 ns propagation delay, making ECL the choice for high-speed prescalers, clock distribution, and RF down-conversion circuits where no other logic family can operate. The power and cooling requirements of ECL boards make them impractical in modern designs except in specialized instrumentation and legacy telecom hardware.

Follow-up: Why does preventing transistor saturation in ECL reduce propagation delay so dramatically compared to TTL?

Q6. How do you interface a 5V TTL output to a 3.3V CMOS input?

A 5V TTL output VOH of 2.4V is below the VIH minimum of a 3.3V CMOS input (typically 0.7 × VDD = 2.31V), which is marginal, so a level shifter like the TXS0108E or a 74LVC buffer with 5V-tolerant inputs that outputs at 3.3V is the correct solution. Connecting a 5V TTL output directly to an STM32 GPIO (which is only 5V-tolerant on selected pins) without a level shifter risks damaging the 3.3V CMOS input on non-tolerant pins. Always check the 5V tolerance marking in the STM32 datasheet pinout table before making a direct connection.

Follow-up: What is a 5V-tolerant CMOS input and what internal protection mechanism enables it to accept 5V signals on a 3.3V device?

Q7. What is BiCMOS and what advantage does it combine from bipolar and CMOS?

BiCMOS integrates both bipolar transistors and CMOS transistors on the same chip, using CMOS logic for high-density low-power internal logic and bipolar transistors for the output drivers to provide high current drive with fast transition edges. The 74BCT logic family (BiCMOS Bus Interface) uses BiCMOS output drivers capable of sinking 64 mA at VOL = 0.5V while the CMOS inputs draw negligible current. BiCMOS is used in high-drive bus buffers and high-speed ADC output drivers where CMOS alone cannot supply sufficient output current without distorting signal edges.

Follow-up: What is the tradeoff in BiCMOS manufacturing cost compared to pure CMOS processes?

Q8. What is the totem-pole output stage in TTL and what problem does it cause in wired-AND configurations?

The totem-pole output connects an active pull-up transistor in series with a pull-down transistor between VCC and ground, providing fast active charging of output capacitance but preventing multiple outputs from being directly wired together because one output's pull-up fights another's pull-down, causing large shoot-through current. Connecting two 74LS totem-pole outputs together can draw over 100 mA of conflict current, potentially burning out both output transistors. Only open-collector or open-drain outputs can be wired together for wired-AND/OR bus configurations.

Follow-up: What value of pull-up resistor would you choose for a 74LS open-collector output driving a 5V bus at 1 MHz?

Q9. What is the difference between 74HC and 74HCT logic?

74HC uses CMOS-compatible input thresholds (VIH ≈ 3.5V at 5V supply) while 74HCT has input thresholds modified to match TTL levels (VIH ≈ 2.0V, VIL ≈ 0.8V), allowing 74HCT devices to accept TTL outputs without level shifting. A 74HCT574 octal flip-flop can be driven directly by 5V TTL outputs from legacy hardware because its thresholds match TTL guaranteed output levels. This makes 74HCT the standard bridge part when replacing TTL ICs in existing PCB designs with CMOS alternatives.

Follow-up: Does substituting 74HC for 74HCT in a TTL-driven circuit always work, and what failure mode occurs if it does not?

Q10. What is power dissipation in CMOS logic and how does it scale with frequency?

CMOS static power is near zero, but dynamic power dissipation equals C × VDD² × f, where C is the load capacitance, VDD is supply voltage, and f is switching frequency. A 74HC gate switching a 10 pF load at 10 MHz on 5V dissipates 0.01 nF × 25V² × 10 MHz = 2.5 mW per gate. This quadratic relationship with VDD is why modern SoCs operate at 0.8–1.2V: halving VDD from 5V to 2.5V reduces dynamic power by 4×.

Follow-up: Besides dynamic and static power, what is the third power component in CMOS gates and when does it dominate?

Q11. What is the difference between open-collector and open-drain outputs?

Open-collector outputs use a bipolar NPN transistor whose collector is left unconnected, while open-drain outputs use an NMOS transistor whose drain is left unconnected; both require an external pull-up resistor and both allow wired-AND connections. A 74LS03 has open-collector outputs for TTL systems, while a 74LVC1G07 has an open-drain output for CMOS and mixed-voltage systems. Open-drain is used in I2C bus lines where multiple devices pull SDA or SCL low independently, with a single pull-up resistor (typically 4.7 kΩ) on each line.

Follow-up: How does the value of the pull-up resistor on an I2C bus affect maximum bus speed?

Q12. What is ground bounce and how does it affect digital circuits?

Ground bounce occurs when multiple output drivers switch simultaneously, causing a large transient current spike through the package inductance of the ground pin that momentarily raises the IC's internal ground potential, inducing false switching on nearby logic inputs. In a 74HC574 octal flip-flop with all 8 outputs switching simultaneously, the 10 nH package inductance with 40 mA/ns switching creates a ground spike of L × di/dt = 10 nH × 40 mA/ns = 400 mV — enough to violate logic thresholds. Adding 100 nF bypass capacitors between VCC and GND at every IC reduces peak ground bounce by providing local charge storage.

Follow-up: What PCB layout technique reduces package inductance and therefore ground bounce in high-speed digital circuits?

Q13. What is the difference between 74AHC and 74VHC logic families?

74AHC (Advanced High-speed CMOS) operates at 2V to 5.5V with propagation delays of about 3.8 ns at 5V and is designed for low-voltage mixed-supply systems, while 74VHC (Very High-speed CMOS) is a higher-speed variant with about 3.5 ns propagation delay at 5V optimized for frequency performance. A 74AHC245 bus transceiver from Texas Instruments handles 1.8V to 5V direction-controlled data paths on modern mixed-voltage PCBs. The AHC family's wide supply range makes it the default choice for new designs bridging 1.8V and 5V domains.

Follow-up: When would you choose 74VHC over 74AHC despite the narrower supply range of VHC?

Q14. What causes latch-up in CMOS ICs and how is it prevented?

Latch-up occurs when a parasitic PNPN thyristor structure inherent in bulk CMOS is triggered by an overvoltage or undershoot on an I/O pin, causing it to latch into a low-impedance state that draws excessive supply current and can destroy the IC. Driving a 3.3V CMOS input above VDD + 0.5V, such as connecting a 5V signal directly to a non-5V-tolerant GPIO, can trigger latch-up in STM32 devices. Prevention includes input clamping diodes, series resistors on inputs, using 5V-tolerant pins, and ensuring PCB power-up sequencing prevents I/O pins from being powered before VDD.

Follow-up: What is the latch-up holding current and why must supply current-limiting be used during latch-up testing?

Q15. What is a Schmitt trigger input and when should it be used on logic gate inputs?

A Schmitt trigger input uses hysteresis — a higher threshold for rising transitions (VT+) and a lower threshold for falling transitions (VT−) — so that slow-rising or noisy signals produce clean output transitions without multiple spurious toggles. A 74HC14 inverter has VT+ ≈ 2.4V and VT− ≈ 1.1V at 5V, giving 1.3V of hysteresis that cleanly digitizes the output of an NTC thermistor voltage divider even with 200 mV of 50 Hz pickup. Schmitt trigger inputs are mandatory on any logic input connected to mechanical switches, slow RC networks, or analog sensor outputs.

Follow-up: What happens if a standard (non-Schmitt) logic input like 74HC04 is connected to a slowly rising signal?