Steady State Error Improvement

Reducing or eliminating steady state error is a practical design objective in control systems. Two primary strategies exist: increasing the open-loop gain and increasing the system type number by adding integrators to the forward path. The second approach, known as integral control, is fundamental to understanding why PID controllers are used so widely in industry.

Core Concept Explanation

For a Type 0 system with step input, the steady state error is ess = 1/(1+Kp) = 1/(1 + K/a). As the gain K is increased, Kp grows large and ess shrinks, but it asymptotically approaches zero and never actually reaches it. To completely eliminate steady state error for a step input, the system type must be raised from 0 to 1 by adding a pole at s = 0, which represents an integrator in the forward path.

Adding an integrator to the controller transforms the control law. Instead of a simple proportional gain, the controller now includes an integral term Ki/s. This is the I-term in a PID controller. The integrator keeps accumulating error over time. As long as any error exists, the integrator output keeps growing, which drives the plant harder until the error is driven to zero.

The physical meaning is powerful. An integrator has infinite DC gain because lim(s->0) 1/s = infinity. Infinite DC gain in the loop means the loop can sustain zero error at DC (constant inputs). This is the mathematical reason why integral action eliminates steady state error.

Mathematical Expression

Consider a plant G_p(s) and a proportional-integral (PI) controller C(s) = Kp + Ki/s = (Kp*s + Ki)/s. The open-loop transfer function becomes G(s) = C(s)*G_p(s). The presence of 1/s in the controller adds one pole at the origin to the loop, increasing the type number of the combined system by 1.

If the original plant is Type 0 and a single integrator is added in the controller, the system becomes Type 1. A Type 1 system has Kp = infinity, giving ess = 1/(1+infinity) = 0 for step inputs. For ramp inputs, the same Type 1 system now has a finite Kv, giving a finite ramp tracking error.

To eliminate ramp tracking error, the type number must be raised to 2 by adding two integrators. However, each additional integrator reduces the phase margin of the system by 90 degrees, making stability progressively more difficult to maintain. This is the fundamental trade-off between steady state accuracy and dynamic stability.

Practical Understanding

In industrial motor speed controllers, integral action is always included because proportional-only control leaves a speed droop under load. The integrator builds up its output over time until the motor reaches exactly the set speed. When the load is suddenly removed, the integrator reduces its output until the speed stabilizes again at the reference.

A critical issue called integrator windup occurs when the actuator saturates (for example, the motor drive is at maximum output) but the error persists. In this condition, the integrator keeps accumulating, building up an enormous output. When saturation ends, the system overshoots badly. Anti-windup circuits are used in real implementations to clamp the integrator when the actuator is saturated.

In cascade control structures used in process industries, the inner loop (fast) uses P-only control and the outer loop (slow) uses PI or PID. This arrangement uses integral action where it is needed most, without compromising the inner loop speed.

Given:
Original plant: G_p(s) = 5 / (s+2),  Type 0
PI controller: C(s) = (s+1) / s
Combined: G(s) = C(s)*G_p(s) = 5(s+1) / [s(s+2)]

Why this formula applies:
System is now Type 1 due to PI controller adding pole at s=0.
Kv = lim(s->0) s*G(s) gives ramp tracking accuracy.

Formula:
Kv = lim(s->0) [s * 5(s+1) / (s(s+2))]
Kv = lim(s->0) [5(s+1) / (s+2)]

Substitution:
Kv = 5 * (0+1) / (0+2)

Calculation:
Kv = 5/2 = 2.5
Step ess = 1/(1+Kp) = 1/(1+inf) = 0
Ramp ess = 1/Kv = 1/2.5

Final Answer with units:
Step steady state error = 0 (perfect tracking)
Ramp steady state error = 0.4 units (finite, not zero)

Exam Tip: Adding one integrator to the controller increases system type number by 1 and eliminates steady state error for one input class (step for Type 0 to 1, ramp for Type 1 to 2). For GATE, remember that PI controller contains one integrator (pole at s=0 in controller), which raises type by 1. Also note: raising type number too high without compensation will destabilize the system.

Mechanism: Integral Control Action

• Increasing gain K reduces step error (ess = 1/(1+K*Kp0)) but cannot eliminate it completely. Only adding a pole at s=0 can achieve zero steady state error.
• Each integrator added to the open-loop forward path increases the type number by 1 and eliminates steady state error for one additional class of inputs.
• A PI controller C(s) = (Kp*s + Ki)/s adds one integrator, raising type number by 1 and ensuring zero steady state error for step inputs.
• Every integrator added to the loop reduces phase by 90 degrees at all frequencies, reducing phase margin and potentially destabilizing the system if not compensated.
• Integrator windup is a real implementation concern. When actuator saturation prevents the integrator from correcting error, the integrator output grows without bound. Anti-windup protection is essential in practical controllers.

Quick Revision

• Gain increase: reduces ess but never achieves zero for step in Type 0 system. ess = 1/(1+Kp).
• Integrator addition: raises type number by 1, completely eliminates steady state error for that input class.
• PI controller = proportional + integral. Adds one pole at s=0 to the open-loop transfer function.
• Each integrator added reduces phase margin by 90 degrees. Stability must be re-verified after type number increase.
• Integrator windup occurs when actuator saturates during large errors. Requires anti-windup implementation.
• Exam trap: adding integrator improves steady state performance but worsens transient stability. Never say integrator always improves system performance.
• Type N system has zero error for step, ramp, ..., up to the N-th order input. Higher order inputs produce infinite error unless type is further raised.