VLSI Design
56 articles • Complete guide
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Curriculum
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MOS Fundamentals
MOSFET physics, IV curves, threshold voltage
MOS Capacitor Structure
Accumulation, depletion, inversion modes.
Threshold Voltage
Expressions, body effect.
NMOS/PMOS I-V
Cutoff, linear, saturation regions.
Channel Length Modulation
Finite output impedance.
Subthreshold Conduction
Leakage current below Vt.
MOS Capacitances
Cgs, Cgd, Cdb, Csb, Cox.
Velocity Saturation
Short channel effect explanation.
Hot Carrier Effect
Reliability issues.
CMOS Logic
Inverter, logic gates, power, noise margins
CMOS Inverter
VTC, noise margins, switching threshold.
CMOS NAND/NOR
Series/Parallel transistor sizing.
Complex Gates
AOI and OAI logic realization.
Pass Transistor Logic
Signal degradation, threshold drop.
Transmission Gates
Perfect switch, resistance analysis.
Tri-State Buffers
High, Low, High-Z states.
Elmore Delay
RC delay estimation.
Logical Effort
Delay optimization technique.
CMOS Circuits
Adders, multipliers, transmission gates
CMOS Adders
Ripple carry, Carry lookahead, Manchester carry chain in CMOS.
Carry Skip/Select
Adder optimization architectures.
CMOS Multipliers
Array multiplier, Wallace tree multiplier basics.
Booth Multiplier
Algorithm for signed multiplication.
Transmission Gate Logic
XOR, Multiplexer implementation using TGs.
Barrel Shifter
Shifting logic using pass transistors.
Domino Logic Circuits
Precharge/Evaluate phases, cascade issues.
Level Shifters
Interfacing different voltage domains.
IO Pads
Input/Output buffers, ESD protection.
Sequential VLSI
Latches, flip-flops, registers, timing
Bistability Principle
Inverter loop, metastability.
SR Latch
NOR and NAND based latches.
D Latch
Level sensitive latch, transmission gate implementation.
D Flip-Flop
Master-Slave edge triggered register.
JK Flip-Flop CMOS
Implementation details.
Setup and Hold Time
Timing constraints, calculating T_clk.
Clock Skew and Jitter
Impact on timing, H-tree clock distribution.
Synchronizers
Handling asynchronous inputs.
Memory Design
SRAM, DRAM, ROM architectures
SRAM 6T Cell
Read stability, write ability.
SRAM Array Org
Row decoders, column muxing.
DRAM 1T Cell
Charge storage, capacitive sensing.
DRAM Refresh
Need for periodic refresh.
Sense Amplifiers
Differential sensing, precharging bitlines.
ROM/PROM Design
Nor-based and Nand-based ROMs.
Flash Memory Cell
Floating gate transistor.
Design Flow
RTL, synthesis, place and route, verification
VLSI Design Flow
Y-Chart, specification to layout steps.
Design Entry
Schematic vs HDL.
Lambda Rules
Scalable design rules, stick diagrams.
Layout Basics
Active, poly, metal layers, contacts.
DRC LVS
Design Rule Check, Layout Vs Schematic.
Parasitic Extraction
R and C extraction for post-layout sim.
Low Power Design
Power analysis, optimization techniques
Other Topics
FinFET, advanced nodes, DFT