Bistability Principle

Sequential logic circuits store binary information by exploiting a fundamental property called bistability. Unlike combinational logic that produces a unique output for each input, bistable circuits have two stable operating points and can remain indefinitely in either state without any external input. Understanding bistability at the transistor level is essential for analyzing latches, flip-flops, and SRAM cells in VLSI design.

The Inverter Loop as a Bistable Element

Consider two CMOS inverters connected in a feedback loop: the output of the first inverter drives the input of the second, and the output of the second inverter feeds back to the input of the first. Each inverter has a voltage transfer characteristic (VTC) that maps an input voltage to an output voltage with a sharp high-gain transition region.

The operating point of the loop is determined by plotting both VTCs on the same axes (one normally, one with axes swapped to represent the feedback). The intersections of the two VTCs are the equilibrium points of the system. A two-inverter loop has exactly three intersections: two stable points (one at Q near VDD, one at Q near GND) and one unstable point near VDD/2. This is the graphical proof of bistability.

At the two stable points, any small perturbation to the node voltage is corrected by the loop gain. If Q is at VDD and is perturbed slightly down, INV2 output rises slightly, which drives INV1 input up, pulling Q back toward VDD. This self-restoring behavior is the defining characteristic of a stable equilibrium. At the metastable point, the loop gain is also greater than 1, but any perturbation causes the state to diverge away from VDD/2 toward one of the two stable states.

Mathematical Expression

The condition for bistability requires that the magnitude of the loop gain at the unstable equilibrium point exceeds unity. The loop gain is the product of the small-signal gains of the two inverters evaluated at their operating point. For a CMOS inverter at VDD/2:

|A_v| = g_m x r_out = (g_m_n + g_m_p) x (r_on || r_op). Bistability exists when A_loop = A_v1 x A_v2 > 1. In practice, for a well-designed CMOS inverter, A_v at the switching point is 20 to 50, so the loop gain far exceeds unity and both stable states are maintained strongly.

The metastability resolution time is the time for the circuit to escape the metastable state and settle to a stable state. This is governed by: V(t) = V_metastable x exp(t / tau), where tau = C_node / (g_m1 + g_m2 - 1/r_out). Smaller tau means faster resolution, which requires larger transconductance.

Practical Understanding

Every memory element in digital design — SR latch, D flip-flop, SRAM cell — is built around the bistable principle. In an SRAM cell, two cross-coupled inverters form the storage element, and the two stable states represent the stored bit. The cell remains in its state indefinitely as long as power is supplied, consuming only leakage current.

Metastability is a practical concern in synchronizers that capture asynchronous signals. When a flip-flop's setup or hold time is violated, the internal nodes are driven to the metastable point. The flip-flop eventually resolves, but the resolution time is random. If resolution takes longer than one clock period, the next stage receives an erroneous value, causing a synchronization failure. Synchronizer circuits use high-gain flip-flops with small tau to minimize mean time between failures (MTBF).

Given:
CMOS inverter at VDD = 1.2V, both NMOS and PMOS at VDD/2 = 0.6V
NMOS: gm_n = 1.2 mA/V, rout_n = 10 kOhm
PMOS: gm_p = 0.8 mA/V, rout_p = 15 kOhm
Node capacitance C = 10 fF

Why this formula applies:
We compute loop gain to verify bistability, then compute tau for metastability resolution.

Formula:
A_v = (gm_n + gm_p) x (rout_n || rout_p)
tau = C / (gm1 + gm2)  (simplified for matched inverters)

Substitution:
rout_n || rout_p = (10k x 15k) / (10k + 15k) = 6 kOhm
A_v = (1.2e-3 + 0.8e-3) x 6000 = 2e-3 x 6000 = 12

A_loop = A_v1 x A_v2 = 12 x 12 = 144 >> 1
Bistability confirmed.

tau = 10e-15 / (2e-3 + 2e-3) = 10e-15 / 4e-3 = 2.5 ps

Final Answer:
Loop gain = 144, confirming strong bistability. Metastability time constant tau = 2.5 ps, meaning the circuit resolves from metastability extremely rapidly.

Exam Tip: GATE often asks how many stable states a two-inverter loop has (answer: 2), or what the metastable state is (V = VDD/2 approximately). Remember: metastability cannot be eliminated by design, only its probability can be reduced by increasing loop gain.

Mechanism of Bistability and Metastability

• Two cross-coupled inverters form a bistable element with exactly two stable states: Q=1/Qb=0 and Q=0/Qb=1.
• Stable states are self-restoring: any perturbation is rejected because the loop gain exceeds unity.
• Metastable state exists at V = VDD/2 where both inverters are at their switching threshold; it is unstable and any noise causes the loop to diverge.
• Metastability time constant tau = C_node / (gm_total); high gm (large transistors) reduces tau and accelerates resolution.
• Synchronizer design uses high-gain flip-flops to minimize tau and reduce the probability of metastability causing a system failure.
• All sequential storage elements (latches, flip-flops, SRAM) exploit bistability; the cross-coupled inverter pair is the fundamental storage primitive.

Quick Revision

• Bistability: two stable operating points in a cross-coupled inverter loop; corresponds to Q=0 and Q=1.
• Three VTC intersections: S0 (Q=GND), S1 (Q=VDD) — stable; Smeta (Q=VDD/2) — unstable.
• Condition for bistability: loop gain A_v1 x A_v2 > 1 (always satisfied in properly designed CMOS inverters).
• Metastability time constant: tau = C_node / g_m_total; smaller tau = faster resolution.
• Metastability escape: V(t) = V_meta x exp(t/tau); exponential divergence from VDD/2.
• GATE trap: metastability cannot be designed away; it can only be made less probable by increasing loop gain (larger transistors, more current).
• SRAM, latches, and flip-flops all use the cross-coupled inverter as their core storage primitive.