SOI Technology

Silicon On Insulator, commonly written as SOI, is a wafer fabrication technology where the active silicon device layer sits on top of a buried oxide layer instead of a bulk silicon substrate. This structure fundamentally changes how transistors behave, reducing parasitic effects that limit the speed and power of conventional bulk CMOS. For GATE and VLSI design courses, SOI is important because it explains how modern high-performance chips push beyond bulk silicon limitations.

Core Concept: Why SOI Exists

In a conventional bulk CMOS transistor, the drain and source regions are diffused directly into the silicon substrate. This creates large junction capacitances between these diffused regions and the substrate. Every time a transistor switches, these capacitances must charge and discharge, consuming dynamic power and slowing the circuit down. Additionally, a current path can form through the substrate between adjacent transistors, creating a destructive condition called latch-up.

SOI eliminates both problems by placing a layer of silicon dioxide, the Buried Oxide (BOX), between the thin active silicon film and the substrate. The device is physically isolated. Junction capacitances drop dramatically because the depletion region cannot extend into the substrate. Latch-up is completely eliminated because the parasitic bipolar path through the substrate no longer exists.

The active silicon film in SOI can be made very thin, typically 50 to 200 nanometers. When the film is thin enough that the depletion region extends fully through it under normal biasing, the device operates in Fully Depleted SOI (FD-SOI) mode. When the film is thicker and a neutral undepleted region remains, it is called Partially Depleted SOI (PD-SOI).

FD-SOI vs PD-SOI Behavior

In PD-SOI, the neutral body region below the channel is electrically floating since the BOX prevents it from contacting the substrate. Charge can accumulate in this floating body, causing shifts in the threshold voltage and producing a phenomenon known as the floating body effect. This effect causes hysteresis in device characteristics and makes circuit behavior less predictable, which is a significant challenge in PD-SOI design.

FD-SOI avoids the floating body effect because the thin film is fully depleted. There is no neutral region to accumulate charge. FD-SOI devices show nearly ideal subthreshold swing approaching 60 mV/decade at room temperature, sharper turn-on characteristics, and better control of short channel effects compared to both PD-SOI and bulk CMOS at the same technology node.

Mathematical Expression

The key metric improved in SOI is the drain junction capacitance. In bulk CMOS the total capacitance at the drain node includes both the gate-drain overlap capacitance and the depletion capacitance of the drain-to-substrate junction. In SOI, the drain-to-substrate junction capacitance is essentially replaced by the much smaller capacitance through the thick BOX. The BOX capacitance per unit area is given by:

C_BOX = epsilon_ox / t_BOX, where epsilon_ox is the permittivity of silicon dioxide (approximately 3.45 x 10^-11 F/m) and t_BOX is the BOX thickness, typically 50 to 150 nm in modern SOI. Since t_BOX is much larger than a typical gate oxide thickness, C_BOX is orders of magnitude smaller than the gate capacitance, meaning the substrate coupling through the BOX is negligible.

Numerical Example

Given:
BOX thickness t_BOX = 100 nm = 100e-9 m
Permittivity of SiO2: epsilon_ox = 3.45e-11 F/m
Device area: A = 1 micrometer x 1 micrometer = 1e-12 m^2

Why this formula applies:
The BOX acts as a parallel plate capacitor between the active layer and the substrate.

Formula:
C_BOX = (epsilon_ox / t_BOX) x A

Substitution:
C_BOX = (3.45e-11 / 100e-9) x 1e-12

Calculation:
C_BOX = (3.45e-11 / 1e-7) x 1e-12
      = 3.45e-4 x 1e-12
      = 3.45e-16 F

Final Answer:
C_BOX = 0.345 aF (attofarads)
This is extremely small, confirming negligible substrate coupling through the BOX.

Practical Implications

SOI technology is widely used in high-performance microprocessors and RF circuits where low parasitic capacitance directly translates to higher operating frequency and lower dynamic power at the same supply voltage. IBM has used SOI since the early 2000s in its server processors. Modern mobile SoCs increasingly adopt FD-SOI, with companies like Samsung and ST Microelectronics offering commercial 28 nm and 22 nm FD-SOI platforms. The back-gate biasing capability in FD-SOI is a unique advantage: by applying a voltage to the substrate below the BOX, the threshold voltage of the device can be tuned dynamically, enabling adaptive power management.

SOI also improves radiation hardness, which is why it is preferred in space and military electronics. Cosmic ray particles passing through bulk silicon generate electron-hole pairs in the substrate that can cause soft errors (bit flips) in memory. The BOX prevents these carriers from reaching the active device region.

Exam Tip: GATE often asks to compare bulk CMOS vs SOI on junction capacitance and latch-up. Remember: SOI eliminates latch-up completely and drastically reduces drain/source junction capacitance because of the BOX. FD-SOI also shows near-ideal subthreshold swing. The floating body effect is a problem specific to PD-SOI, not FD-SOI.

• The BOX layer in SOI acts as a physical isolation barrier between the active transistor and the bulk substrate.
• Junction capacitance is reduced because the depletion region is confined to the thin active film and cannot extend into the substrate.
• Latch-up is fully eliminated since the parasitic pnpn structure requires a substrate current path that no longer exists.
• FD-SOI uses a thin enough film that the body is always depleted, removing the floating body problem seen in PD-SOI.
• The back-gate effect in FD-SOI allows threshold voltage tuning by biasing the substrate below the BOX.

Quick Revision

• SOI places the active device layer on a Buried Oxide (BOX), isolating it from the substrate.
• Key advantages: reduced junction capacitance, no latch-up, lower dynamic power, better short-channel control.
• FD-SOI: film fully depleted, no floating body effect, near-ideal subthreshold swing ~60 mV/decade.
• PD-SOI: neutral body region exists, floating body effect causes threshold voltage instability.
• C_BOX = epsilon_ox / t_BOX; large t_BOX means negligible substrate coupling capacitance.
• SOI is radiation hard: BOX blocks substrate-generated carriers from reaching active devices.
• Exam trap: Do not confuse floating body effect (PD-SOI issue) with FD-SOI, which does not have this problem.