Transmission Gates

In CMOS digital design, connecting two signal paths cleanly without logic inversion requires a special structure. The transmission gate fulfills this role by combining an NMOS and PMOS transistor in parallel, enabling bidirectional signal flow with near-ideal switch behavior across the full voltage range.

Unlike a single NMOS pass transistor which degrades logic-1 by a threshold voltage Vtn, the transmission gate passes both logic-0 and logic-1 without degradation. This makes it fundamental in multiplexers, XOR gates, D latches, and datapath circuits in modern VLSI.

Core Concept Explanation

A transmission gate is formed by placing one NMOS transistor and one PMOS transistor in parallel between two terminals A and B. The NMOS gate is driven by CLK and the PMOS gate is driven by CLK_B, the complement of CLK. When CLK is high, both transistors turn on simultaneously, creating a low-resistance path from A to B.

The key insight is complementary coverage. An NMOS transistor conducts strongly for logic-0 inputs but degrades at logic-1 because it cannot pull the output above Vdd - Vtn. A PMOS transistor does the opposite: it passes logic-1 well but degrades at logic-0. By connecting both in parallel with complementary gate signals, the two transistors cover each other's weakness across the full swing.

The on-resistance of the transmission gate is the parallel combination of NMOS resistance Rn and PMOS resistance Rp. Since Rn increases toward logic-1 and Rp decreases, and vice versa toward logic-0, their parallel combination remains relatively flat and low across the entire voltage range. This is the fundamental advantage over a single pass transistor.

Mathematical Expression

The on-resistance of a single NMOS pass transistor in the linear region is given by:

R_on_N = 1 / (mu_n * Cox * (W/L) * (Vgs - Vtn))

For the transmission gate, the effective resistance seen between A and B is the parallel combination:

R_TG = (R_on_N * R_on_P) / (R_on_N + R_on_P)

As the input voltage Vin varies from 0 to Vdd, R_on_N increases while R_on_P decreases, and their parallel result stays bounded. This ensures signal integrity for both logic levels. The propagation delay through a transmission gate driving a load capacitance C is approximately 0.69 * R_TG * C, following standard RC delay analysis.

Practical Understanding

Transmission gates appear in almost every practical CMOS datapath. In a 2-to-1 multiplexer, two transmission gates with complementary select signals route one of two data inputs to the output. In D latches and flip-flops, a transmission gate forms the transparent window that allows data to pass during the active clock phase and blocks it otherwise.

In XOR and XNOR implementations, transmission gates reduce the transistor count compared to static CMOS. A 2-input XOR realized using transmission gates requires only 6 transistors instead of the 12 needed in full static CMOS, which is a significant area saving in arithmetic circuits.

The main limitation of transmission gates is that they introduce resistance in series with the signal path. In a chain of transmission gates, this resistance accumulates. Long chains are therefore avoided or periodically buffered. The PMOS transistor also adds area and capacitance compared to a pure NMOS pass network, so designers choose based on speed versus swing requirements.

Given:
Vdd = 1.8 V, Vtn = 0.4 V, |Vtp| = 0.4 V
mu_n * Cox * (W/L)_N = 200 uA/V^2
mu_p * Cox * (W/L)_P = 100 uA/V^2
Input voltage Vin = 0.9 V (midpoint), Load C = 50 fF

Why this formula applies:
At Vin = 0.9 V, both NMOS and PMOS are in the linear region.
Vgs_N = Vdd - Vin = 0.9 V (NMOS gate = Vdd), overdrive = 0.9 - 0.4 = 0.5 V
Vgs_P = 0 - Vin = -0.9 V (PMOS gate = 0), overdrive = 0.9 - 0.4 = 0.5 V

Formula:
R_on_N = 1 / (kn * Vov_N)  where kn = mu_n*Cox*(W/L)_N
R_on_P = 1 / (kp * Vov_P)
R_TG = R_on_N || R_on_P

Substitution:
R_on_N = 1 / (200e-6 * 0.5) = 1 / 100e-6 = 10 kOhm
R_on_P = 1 / (100e-6 * 0.5) = 1 / 50e-6  = 20 kOhm

Calculation:
R_TG = (10k * 20k) / (10k + 20k) = 200k / 30k = 6.67 kOhm
Delay = 0.69 * 6.67e3 * 50e-15

Final Answer:
R_TG = 6.67 kOhm, Propagation delay = 0.23 ps

Exam Tip: GATE often asks why a single NMOS pass transistor cannot pass logic-1 fully. Answer: the output is limited to Vdd - Vtn because once Vout rises to Vdd - Vtn, Vgs of NMOS falls to Vtn and the transistor cuts off. A transmission gate avoids this because PMOS takes over near logic-1.

• NMOS resistance increases as input rises toward Vdd because overdrive Vgs - Vtn decreases.
• PMOS resistance decreases as input rises because its overdrive increases toward Vdd.
• Parallel combination keeps R_TG low and flat, ensuring full-swing signal passing.
• CLK=1 enables the gate; CLK=0 turns off both transistors, creating high-impedance state.
• Used in MUX, D latch, XOR, and arithmetic cells for area-efficient switching.

Quick Revision

• Transmission gate = NMOS || PMOS with complementary gate signals CLK and CLK_B.
• Single NMOS degrades logic-1 by Vtn; PMOS covers the high-voltage region in TG.
• R_TG = R_on_N || R_on_P, which stays flat across input voltage range.
• Delay = 0.69 * R_TG * C_load for step input driving a capacitive load.
• TG-based 2:1 MUX requires fewer transistors than static CMOS equivalent.
• Chaining multiple TGs adds series resistance; buffer insertion is needed for long chains.
• Exam trap: TG is bidirectional and has no logic inversion, unlike a standard CMOS inverter.