Tri-State Buffers

In digital systems, multiple devices often share a common bus. If every driver actively drives the bus to a logic level simultaneously, contention and excessive current result. The tri-state buffer solves this by introducing a third output state: the high-impedance state, commonly called Hi-Z, which electrically disconnects the driver from the bus.

Tri-state buffers are found in memory data buses, microprocessor data paths, and any architecture where multiple blocks must share a common wire. Understanding their three states: logic-0, logic-1, and high-impedance is fundamental to bus design and GATE-level digital circuits.

Core Concept Explanation

A tri-state buffer has two inputs: a data input A and an enable signal EN. When EN is active (EN=1 for active-high enable), the buffer behaves like a standard non-inverting buffer: output Y equals input A. When EN is inactive (EN=0), the output is placed in the high-impedance state, effectively disconnecting the output terminal from the circuit electrically.

The high-impedance state does not mean the output is at a mid-voltage. It means the output transistors are both turned off. No current flows from supply or ground through the output stage. From the perspective of any other device connected to the same wire, the tri-state buffer has simply ceased to exist on that node when disabled.

In CMOS implementation, a tri-state buffer is built from a standard CMOS inverter with an additional NMOS transistor in series with the pull-down and an additional PMOS transistor in series with the pull-up. When EN is low, both added transistors turn off and the output floats. When EN is high, both transistors are on and the core inverter drives the output, often with a second stage inversion to make it a non-inverting buffer overall.

Mathematical Expression

The logic function of a tri-state buffer with active-high enable can be expressed as:

Y = A when EN = 1

Y = Z when EN = 0 (Z denotes high-impedance)

For a tri-state inverter, the expression becomes Y = A_bar when EN=1, else Z. The output impedance in the active state is the on-resistance of the output transistors, typically a few hundred ohms to a few kilohms. In the Hi-Z state, the output impedance is essentially the leakage resistance of the off transistors, which is many megaohms. The ratio of off-resistance to on-resistance must be very high for proper bus operation.

Practical Understanding

In a shared bus architecture, multiple tri-state buffers connect their outputs to the same wire. The system ensures that at most one buffer is enabled at any time, controlled by a bus arbiter or address decoder. If two tri-state outputs attempt to drive opposite logic levels simultaneously, a bus fight occurs causing large short-circuit current and potentially corrupting data.

The bus hold circuit or weak keeper is often placed on shared buses to prevent the floating state from drifting to an indeterminate voltage due to noise when all tri-state drivers are disabled. This keeper uses a very weak inverter in a feedback loop that lightly holds the last driven value.

Tri-state buffers are also used in bidirectional I/O pads of ICs. A pad can act as an input when its tri-state driver is disabled, and as an output when enabled. This is how microcontroller GPIO pins work in practice.

Given:
Tri-state buffer output stage: PMOS W/L = 4, NMOS W/L = 2
mu_p * Cox = 50 uA/V^2, mu_n * Cox = 100 uA/V^2
Vdd = 1.8 V, Vtp = -0.4 V, Vtn = 0.4 V
Load capacitance C = 100 fF, output driving Y = 1 (pull-up active)

Why this formula applies:
When EN=1 and A=0 (active-high buffer: PMOS pulls up, NMOS in series is ON)
PMOS Vsg = Vdd = 1.8 V, overdrive = 1.8 - 0.4 = 1.4 V
Series enable NMOS Vgs = Vdd = 1.8V, overdrive = 1.8 - 0.4 = 1.4 V

Formula:
R_p = 1 / (mu_p * Cox * (W/L)_p * Vov_p)
R_en_N = 1 / (mu_n * Cox * (W/L)_N * Vov_N)
R_total = R_p + R_en_N (series)

Substitution:
R_p     = 1 / (50e-6 * 4 * 1.4) = 1 / 280e-6 = 3.57 kOhm
R_en_N  = 1 / (100e-6 * 2 * 1.4) = 1 / 280e-6 = 3.57 kOhm

Calculation:
R_total = 3.57 + 3.57 = 7.14 kOhm
Delay   = 0.69 * 7.14e3 * 100e-15

Final Answer:
R_total = 7.14 kOhm, Propagation delay (rising) = 0.49 ps

Exam Tip: In GATE problems involving bus wiring, remember Hi-Z is not logic-0 and not logic-1. It is electrically floating. A node left floating can drift to any voltage. Always identify whether a pull-up or keeper holds the bus when all drivers are disabled.

• EN=0 turns off both the PMOS_EN series transistor and NMOS_EN series transistor simultaneously.
• With both output-stage paths broken, output node Y becomes electrically floating (Hi-Z).
• EN=1 activates the series enable transistors, restoring normal CMOS push-pull operation.
• Four transistors total: two for the core inverter logic and two for enable control.
• Bus contention occurs when two tri-state drivers with opposite data are enabled simultaneously.

Quick Revision

• Three states: Logic-1, Logic-0, and Hi-Z (high impedance, electrically disconnected).
• Y = A when EN=1; Y = Z when EN=0 for active-high non-inverting tri-state buffer.
• CMOS implementation uses 4 transistors: 2-core inverter plus 2-enable series transistors.
• Hi-Z state does not mean 0 V; it means output stage is fully off and floating.
• Bus contention (bus fight) occurs when two outputs drive opposite values on same wire.
• Keeper or pull-up resistor prevents bus from floating to indeterminate level in Hi-Z.
• Exam trap: Do not confuse tri-state buffer with open-drain output; they have different mechanisms.