Complex Gates

Beyond basic NAND and NOR gates, CMOS technology allows direct realization of complex Boolean functions in a single gate stage using structured pull-up and pull-down networks. Complex CMOS gates such as AOI (And-Or-Invert) and OAI (Or-And-Invert) are routinely used in standard cell libraries because they implement multi-level logic in a single complementary network pair, reducing transistor count, delay, and area compared to cascaded simple gates.

Core Concept Explanation

Every CMOS logic gate — simple or complex — follows the same fundamental rule: the Pull-Down Network (PDN) is made of nMOS transistors that implement a Boolean function F(inputs) at the output, and the Pull-Up Network (PUN) is the exact dual network in pMOS that implements the complement. Because the output is always taken at the junction of PUN and PDN, the gate output equals the logical complement of whatever Boolean function the PDN implements. This is why complex gates are always inverting: AND-OR becomes AND-OR-Invert (AOI), and OR-AND becomes OR-AND-Invert (OAI).

An AOI (And-Or-Invert) gate implements the function Y = NOT(A·B + C·D + ...). The PDN of an AOI-21 (two inputs ANDed, one separate input) contains A and B nMOS transistors in series (implementing A AND B in the pull-down), connected in parallel with a single C transistor. This PDN structure implements AB+C in the pull-down, so the output Y = NOT(AB + C).

An OAI (Or-And-Invert) gate implements Y = NOT((A+B)·(C+D)·...). The PDN of an OAI-21 contains a parallel combination of A and B nMOS (implementing A OR B), connected in series with a single C transistor. This PDN implements (A+B)·C in the pull-down, giving Y = NOT((A+B)·C).

The motivation for using complex gates over equivalent multi-stage implementations is primarily reduced transistor count and delay. An AOI-21 gate requires only 5 transistors (2 nMOS series + 1 nMOS parallel + 2 pMOS parallel + 1 pMOS series = 5 total: 3 nMOS, 2 pMOS) compared to 8 transistors needed for a separate AND gate followed by an OR gate followed by an inverter. The single-stage implementation also eliminates one logic stage delay.

Constructing Complex Gates from Boolean Expressions

The systematic method for constructing a complex gate from a Boolean function proceeds in three steps. First, write the desired output function in its inverted form, for example Y = NOT(AB + CD). Second, construct the PDN by directly reading the expression inside the NOT: each AND term becomes a series connection of nMOS transistors, and each OR of terms becomes a parallel connection of those series groups. Third, construct the PUN as the dual of the PDN by swapping series for parallel and replacing each nMOS with a pMOS transistor connected to VDD.

The PUN can also be constructed algebraically. The complement of Y is (AB + CD), and by DeMorgan's theorem the PUN implements NOT(AB+CD) = (NOT_A + NOT_B)(NOT_C + NOT_D) in terms of when the pMOS transistors are ON (pMOS is ON when its gate is LOW). Practically, each pMOS gate is connected to the same input as the corresponding nMOS gate, and the series-parallel structure mirrors the dual. This dual construction guarantees that PUN and PDN are never simultaneously ON and always complementary.

Practical Understanding

Complex gates are heavily used in critical timing paths where minimizing logic depth (number of gate stages) is essential. In adder carry chains, multiplexer trees, and priority encoders, AOI and OAI gates reduce the stage count and thus the worst-case path delay. Modern synthesis tools automatically recognize Boolean functions that can be mapped to complex gate cells in the standard cell library.

The sizing of complex gates follows the same series stack rule as NAND and NOR. Each transistor in a series chain of N devices must be N× wider than the reference inverter transistor. The worst-case sizing is determined by the longest series path in the PDN or PUN. For an AOI-22 (Y = NOT(AB + CD)), the longest PDN path is 2 series nMOS, so each nMOS must be 2× the reference width. The PUN also has a 2-transistor series path (for the dual structure), so each pMOS in that series path must be 2× the reference pMOS width.

One important limitation of complex gates is that high fan-in increases series depth, which raises threshold voltage issues due to body effect in the deeper transistors of the stack and increases the total resistance of the pull-down or pull-up path. In practice, complex gates with more than 4–5 inputs per series path become impractical and are replaced by multi-stage implementations.

Given:
Implement Y = NOT(A·B·C + D) using a complex AOI gate.
Reference inverter sizing: Wn = 1µm, Wp = 2µm (mobility ratio = 2)

Why this formula applies:
PDN implements ABC + D in pull-down. Longest series path = 3 nMOS (A, B, C in series).
Sizing rule: W = N × W_reference for N transistors in series.

PDN construction:
- A, B, C nMOS in series (3-transistor stack) implements ABC
- D nMOS in parallel with the ABC stack implements ABC + D

PUN construction (dual):
- A, B, C pMOS in parallel (any single pMOS ON pulls output high)
- D pMOS in series with the parallel group

Transistor Sizing:
Longest PDN series path = 3 → W_nMOS = 3 × 1µm = 3µm (for A, B, C nMOS)
D nMOS (standalone): W = 1µm (single transistor, no series)
Longest PUN series path = 1 (D pMOS, only series device) → W_pMOS_D = 1 × 2µm = 2µm
A, B, C pMOS (parallel): W = 2µm each (no series penalty)

Total transistors: 4 nMOS + 4 pMOS = 8 transistors for a 4-input function

Final Answer:
nMOS widths: A=3µm, B=3µm, C=3µm, D=1µm
pMOS widths: A=2µm, B=2µm, C=2µm, D=2µm
Vs. cascade (NAND3 + NAND2 + INV) = 14 transistors — AOI saves 6 transistors.

Exam Tip: For GATE complex gate problems, always identify the longest series path to determine the worst-case sizing. For an AOI gate, the critical sizing is in the nMOS series stack (PDN). For an OAI gate, it is in the pMOS series stack (PUN). The output always equals the complement of what the PDN implements.

Mechanism and Design Summary

The following points summarize the key construction and analysis rules for complex CMOS gates.

• Complex gates are always inverting: AOI output = NOT(AND-OR expression), OAI output = NOT(OR-AND expression).
• PDN construction rule: AND terms in the Boolean expression inside NOT become series nMOS chains; OR between terms becomes parallel connections of those chains.
• PUN is always the dual of PDN: replace each series connection with parallel and each nMOS with pMOS connected to VDD.
• Sizing: transistors in an N-long series stack must be N× wider than the reference. Parallel transistors need no additional sizing.
• AOI gates are preferred in timing-critical paths because their series nMOS stacks are more efficient than equivalent OAI series pMOS stacks.
• Practical fan-in limit is 4–5 inputs per series path due to body effect and increasing resistance in deeper stacks.

Quick Revision

• AOI-21: Y = NOT(AB + C). PDN: (A series B) parallel C. PUN: (A parallel B) series C (dual).
• OAI-21: Y = NOT((A+B)·C). PDN: (A parallel B) series C. PUN: (A series B) parallel C (dual).
• Output is always inverted — the gate output = NOT(function implemented in PDN).
• Sizing: longest series path of N transistors → each transistor width = N × W_reference.
• Complex gates save transistors and reduce logic stages compared to equivalent cascaded NAND/NOR/INV implementations.
• AOI preferred over OAI: series nMOS (higher mobility) is less penalizing than series pMOS.
• GATE trap: The PUN is NOT built by writing the complement of the PDN Boolean expression — it is built as the structural dual (series ↔ parallel swap) of the PDN topology.